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integrated power solution with quad buck regulators, supervisory, and i 2 c interface preliminary technical data ADP5051 rev. prb document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its us e. specifications subject to change without notice. no license is granted by implication or otherwise unde r any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective owners. one technology way, p.o. box 9106, norwood, ma 0206 29106, u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all ri ghts reserved. technical support www.analog.com features wide input voltage range: 4.5 v to 15.0 v 1.5% output accuracy over full temperature range 250 khz to 1.4 mhz adjustable switching frequency adjustable/fixed output options via factory fuse or i 2 c interface i 2 c interface with interrupt on fault conditions power regulation channel 1 and channel 2: programmable 1.2 a/2.5 a/4 a sync buck regulators with lowside fet driver channel 3 and channel 4: 1.2 a sync buck regulators single 8 a output (channel 1 and channel 2 in paral lel) dynamic voltage scaling (dvs) for channel 1 and cha nnel 4 precision enable with 0.8 v accurate threshold active output discharge switch programmable phase shift in 90 steps individual channel fpwm/psm selection frequency synchronization input or output optional latchoff protection on ovp/ocp failure powergood flag on selected channels low input voltage detection opendrain processor reset with external adjustable threshold monitoring watchdog refresh input manual reset input overheat detection on junction temperature uvlo, ocp, and tsd protection applications small cell base stations fpga and processor applications security and surveillance medical applications general description the ADP5051 combines four high performance buck regulators, and a supervisory circuit with a voltage monitor, w atchdog, and manual reset in a 48lead lfcsp package that meets demanding performance and board space requirements. the devic e enables direct connection to high input voltages up to 15.0 v with no preregulators. channel 1 and channel 2 integrate highside power m osfet and lowside mosfet drivers. in lowside power devices, use external nfets to achieve an efficiency optimized solution a nd deliver a programmable output current of 1.2 a, 2.5 a, or 4 a . typical application circuit channel 2 buck (4a) channel 3 buck (1.2a) oscillator int vreg 100ma q1 q2 l1 l2 vreg l3 alert l4 c2 c1 c4 c3 c5 c6 c7 c8 c9 c10 c11 c12 c13 4.5v to 15v vout1 vout2 vout3 vout4 r ilim1 r ilim2 i 2 c vreg exposed pad c0 watchdog and reset vreg pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 vddio pvin4 comp4 en4 scl sda ss12 vdd wdi mr sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 bst3 sw3 fb3 pgnd3 bst4 sw4 fb4 pgnd4 int pwrgd vth rsto vreg voutx ADP5051 channel 1 buck (4a) channel 4 buck (1.2a) 11635-001 figure 1. combining channel 1 and channel 2 in a parallel conf iguration provides a single output with up to 8 a of current. channel 3 and channel 4 integrate both highside and lowside mos fets to deliver an output current of 1.2 a. the ADP5051 supervisory circuits monitor voltage level. the watchdog timer generates a reset when the wdi does not toggle within a preset timeout period. select manual reset functionality via the processor reset mode or system power on/off switch mode. the optional i 2 c interface offers flexible configurations, includi ng adjustable and fixed output voltage, junction tempe rature overheat warning, low input voltage detection, and dynamic v oltage scaling. table 1. family models model channels i 2 c package adp5050 four buck, one ldo yes 48lead lfcsp ADP5051 four buck, supervisory yes 48lead lfcsp adp5052 four buck, one ldo no 48lead lfcsp adp5053 four buck, supervisory no 48lead lfcsp
ADP5051 preliminary technical data rev. prb | page 2 of 63 table of contents features .......................................... ................................................... .. 1 applications ...................................... ................................................. 1 general description ............................... ........................................... 1 typical application circuit ....................... ....................................... 1 revision history .................................. .............................................. 3 functional block diagram .......................... ..................................... 4 specifications .................................... ................................................. 5 buck regulator specifications ..................... ................................ 6 supervisory specifications ........................ ................................... 8 i 2 c interface timing specifications ................. ........................... 9 absolute maximum ratings .......................... ................................ 10 thermal resistance ................................ ..................................... 10 esd caution ....................................... ......................................... 10 pin configuration and function descriptions ....... .................... 11 typical performance characteristics ............... ............................. 13 theory of operation ............................... ........................................ 19 buck regulator operational modes .................. ....................... 19 adjustable and fixed output voltages .............. ....................... 20 dynamic voltage scaling (dvs) ..................... .......................... 20 internal regulators (vreg and vdd) ................ .................... 20 separate supply applications....................... .............................. 20 lowside device selection.......................... ............................... 20 bootstrap circuitry ............................... ...................................... 21 active output discharge switch .................... ........................... 21 precision enabling ................................ ...................................... 21 oscillator ........................................ .............................................. 21 synchronization input/output ...................... ............................ 22 soft start ........................................ ............................................... 22 parallel operation ................................ ....................................... 23 startup with precharged output .................... ........................... 23 current limit protection .......................... ................................. 24 frequency foldback ................................ .................................... 24 hiccup protection ................................. ...................................... 24 latchoff protection............................... .................................... 24 undervoltage lockout (uvlo) ....................... ......................... 25 powergood function ............................... ................................. 25 interrupt function ................................ ...................................... 25 thermal shutdown .................................. ................................... 26 overheat detection ................................ .................................... 26 low input voltage detection ....................... ............................. 26 supervisory ....................................... ........................................... 26 i 2 c interface ....................................... .............................................. 29 sda and scl pins .................................. ..................................... 29 i 2 c addresses ....................................... ........................................ 29 selfclear register bits .......................... ..................................... 29 i 2 c interface timing diagrams ....................... .......................... 30 applications information .......................... ..................................... 31 adisimpower design tool ........................... ............................. 31 programming the adjustable output voltage ......... ................ 31 voltage conversion limitations .................... ........................... 31 current limit setting ............................. .................................... 31 soft start setting ................................ ......................................... 32 inductor selection ................................ ....................................... 32 output capacitor selection ........................ ............................... 32 input capacitor selection ......................... ................................. 33 lowside power device selection ................... ......................... 33 programming the uvlo input ........................ ........................ 33 compensation components design .................... .................... 34 power dissipation ................................. ...................................... 34 junction temperature .............................. ................................... 36 design example .................................... ........................................... 37 setting the switching frequency ................... ........................... 37 setting the output voltage ........................ ................................ 37 setting the current limit ......................... .................................. 37 selecting the inductor ............................ .................................... 37 selecting the output capacitor .................... ............................. 37 selecting the lowside mosfet ..................... ........................ 38 designing the compensation network ................ ................... 38 selecting the soft start time ..................... ................................ 38 selecting the input capacitor ..................... ............................. 388 recommended external components ................... .................. 38 circuit board layout recommendations .............. ...................... 41 typical application circuits ...................... .................................... 42 register map ...................................... .............................................. 45 detailed register descriptions .................... .................................. 46
preliminary technical data ADP5051 rev. prb | page 3 of 63 register 1: pctrl (channel enable control), address 0x01 ........................................ ....................................... 46 register 2: vid1 (vid setting for channel 1), address 0x02 ........................................ ....................................... 46 register 3: vid23 (vid setting for channel 2 and channel 3), address 0x03 ............................. ............................. 47 register 4: vid4 (vid setting for channel 4), address 0x04 ........................................ ....................................... 47 register 5: dvs_cfg (dvs configuration for channel 1 and channel 4), address 0x05 ............................. ............................. 48 register 6: opt_cfg (fpwm/psm mode and output discharge function configuration), address 0x06 ..... ............. 49 register 7: lch_cfg (shortcircuit latchoff and ov ervoltage latchoff configuration), address 0x07 .............. ..................... 50 register 8: sw_cfg (switching frequency and phase sh ift configuration), address 0x08 ........................ ........................... 50 register 9: th_cfg (temperature warning and low v in warning threshold configuration), address 0x09 ...... ......... 51 register 10: hiccup_cfg (hiccup configuration), address 0x0a ........................................ ...................................... 52 register 11: pwrgd_mask (channel mask configuration for pwrgd pin), address 0x0b ....................... ....................... 53 register 12: lch_status (latchoff status readback), address 0x0c ........................................ ...................................... 53 register 13: status_rd (status readback), address 0x0d ........................................ ...................................... 54 register 14: int_status (interrupt status readback), address 0x0e ........................................ ....................................... 55 register 15: int_mask (interrupt mask configuration), address 0x0f ........................................ ....................................... 55 register 16: force_shut (forced shut down), address 0x 10 . 56 register 17: default_set (default reset), address 0x11 . 56 factory programmable options ...................... ............................. 57 factory default options ........................... ................................. 59 outline dimensions ................................ ....................................... 60 ordering guide .................................... ....................................... 60
ADP5051 preliminary technical data rev. prb | page 4 of 63 functional block diagram + ? + ? q1 uvlo1 vreg vreg pvin1 sw1 bst1 dl1 driver driver pgnd en1 1m + ? ocp comp1 fb1 clk1 pwrgd1 0.72v zero cross + ? + ? + ? + ? channel 1?buck channel 2?buck channel 3?buck channel 4?buck duplicate channel 3 duplicate channel 1 supervisory current balance en2 comp2 fb2 dl2 pvin2 sw2 bst2 + ? ea1 vid1 rt oscillator sync/mode ss12 ss34 vdd vreg vddio scl sda vreg pvin1 0.5v power-on reset pwrgd int + ? pvin3 sw3 bst3 driver driver zero cross pgnd3 en3 + ? comp3 fb3 + ? + ? + ? en4 comp4 fb4 pgnd4 pvin4 sw4 bst4 + ? wdi rsto mr vth + ? house-keeping logic 0.8v 1m clk3 0.8v 0.8v control logic and mosfet driver with anticross protection control logic and mosfet driver with anticross protection discharge switch a cs1 uvlo3 vreg vreg current limit selection slope comp hiccup and latch-up ovp latch-up cmp1 clk1 0.8v 0.88v freq foldback soft-start decoder internal regulator i2c and registers q3 q4 discharge switch ocp hiccup and latch-up ea3 cmp3 clk3 pwrgd3 0.72v vid3 ovp latch-up 0.88v slope comp freq foldback a cs3 reset generator watchdog detector debounce 11635-100 figure 2. detailed functional block diagram
preliminary technical data ADP5051 rev. prb | page 5 of 63 specifications v in = 12 v, v vreg = 5.1 v, t j = ?40c to +125c for minimum and maximum specications , and t a = 25c for typical specifications, unless otherwise noted. table 2. parameter symbol min typ max unit test conditions/c omments input supply voltage range v in 4.5 15.0 v pvin1, pvin2, pvin3, pvin4 pins quiescent current pvin1, pvin2, pvin3, pvin4 p ins operating quiescent current i q 4.8 6.35 ma no switching, all enx pins high i shdn 25 65 a all enx pins low undervoltage lockout uvlo pvin1, pvin2, pvin3, pvin4 pins threshold rising v uvlorising 4.2 4.36 v falling v uvlofalling 3.6 3.78 v hysteresis v hys 0.42 v oscillator circuit switching frequency f sw 700 740 780 khz rt = 25.5 k range 250 1400 khz sync input input clock range f sync 250 1400 khz input clock pulse width minimum on time t sync_min_on 100 ns minimum off time t sync_min_off 100 ns input clock high voltage v h (sync) 1.3 v input clock low voltage v l (sync) 0.4 v sync output clock frequency f clk f sw khz positive pulse duty cycle t clk_pulse_duty 50 % rise or fall time t clk_rise_fall 10 ns high level voltage v h(sync_out) v vreg v precision enabling en1, en2, en3, en4 pins high level threshold v th_h (en) 0.806 0.832 v low level threshold v th_l (en) 0.688 0.725 v pulldown resistor r pulldown (en) 1.0 m power good internal power good rising threshold v pwrgd (rise) 86.3 90.5 95 % hysteresis v pwrgd (hys) 3.3 % falling delay t pwrgd_fall 50 s rising delay for pwrgd pin t pwrgd_pin_rise 1 ms leakage current for pwrgd pin i pwrgd_leakage 0.1 1 a output low voltage for pwrgd pin v pwrgd_low 50 100 mv i pwrgd = 1 ma logic inputs (scl and sda pins) vddio = 3.3 v threshold level high v logic_high 0.7 vddio v low v logic_low 0.3 vddio v logic outputs low level output voltage sda pin v sda_low 0.4 v vddio = 3.3 v, i sda = 3 ma int pin v int _low 0.4 v i int = 3 ma
ADP5051 preliminary technical data rev. prb | page 6 of 63 parameter symbol min typ max unit test conditions/c omments internal regulators vdd output voltage v vdd 3.2 3.305 3.4 v i vdd = 10 ma current limit i lim_vdd 20 51 80 ma vreg output voltage v vreg 4.9 5.1 5.3 v dropout voltage v dropout 225 mv i vreg = 50 ma current limit i lim_vreg 50 95 140 ma low input voltage detection threshold v lvinth 4.07 4.236 4.39 v lvin_th[3:0] = 0000 10.05 10.25 10.4 v lvin_th[3:0] = 1100 threshold range 4.2 11.2 v i 2 c programmable (4bit value) thermal shutdown (tsd) threshold t shdn 150 c hysteresis t hys 15 c thermal overheat warning threshold t hot 115 c temp_th[1:0] = 10 threshold range 105 125 c i 2 c programmable (2bit value) hysteresis t hot (hys) 5 c buck regulator specifications v in = 12 v, v vreg = 5.1 v, f sw = 600 khz for all channels, t j = ?40c to +125c for minimum and maximum specificatio ns, and t a = 25c for typical specifications, unless otherwise noted. table 3. parameter symbol min typ max unit test conditions/c omments channel 1 sync buck regulator fb1 pin fixed output options v out1 0.85 1.60 v fuse trim or i 2 c interface (5bit value) adjustable feedback voltage v fb1 0.800 v feedback voltage accuracy v fb1 (default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb1 0.1 a adjustable voltage sw1 pin highside power fet on resistance r dson (1h) 100 m pintopin measurement current limit threshold i th (ilim1) 3.50 4.4 5.28 a r ilim1 = floating 1.91 2.63 3.08 a r ilim1 = 47 k 4.95 6.44 7.48 a r ilim1 = 22 k minimum on time t min_on1 117 155 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off1 1/9 t sw ns f sw = 250 khz to 1.4 mhz lowside driver, dl1 pin rising time t rising1 20 ns c iss = 1.2 nf falling time t falling1 3.4 ns c iss = 1.2 nf sourcing resistor t sourcing1 10 sinking resistor t sinking1 0.95 error amplifier (ea), comp1 pin ea transconductance g m1 310 470 620 s
preliminary technical data ADP5051 rev. prb | page 7 of 63 parameter symbol min typ max unit test conditions/c omments soft start soft start time t ss1 2.0 ms ss12 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup1 7 t ss1 ms c out discharge switch on resistance r dis1 250 channel 2 sync buck regulator fb2 pin fixed output options v out2 3.3 5.0 v fuse trim or i 2 c interface (3bit value) adjustable feedback voltage v fb2 0.800 v feedback voltage accuracy v fb2(default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb2 0.1 a adjustable voltage sw2 pin highside power fet on resistance r dson(2h) 110 m pintopin measurement currentlimit threshold i th(ilim2) 3.50 4.4 5.28 a r ilim2 = floating 1.91 2.63 3.08 a r ilim2 = 47 k 4.95 6.44 7.48 a r ilim2 = 22 k minimum on time t min_on2 117 155 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off2 1/9 t sw ns f sw = 250 khz to 1.4 mhz lowside driver, dl2 pin rising time t rising2 20 ns c iss = 1.2 nf falling time t falling2 3.4 ns c iss = 1.2 nf sourcing resistor t sourcing2 10 sinking resistor t sinking2 0.95 error amplifier (ea), comp2 pin ea transconductance g m2 310 470 620 s soft start soft start time t ss2 2.0 ms ss12 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup2 7 t ss2 ms c out discharge switch on resistance r dis2 250 channel 3 sync buck regulator fb3 pin fixed output options v out3 1.20 1.80 v fuse trim or i 2 c interface (3bit value) adjustable feedback voltage v fb3 0.800 v feedback voltage accuracy v fb3(default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb3 0.1 a adjustable voltage sw3 pin highside power fet on resistance r dson(3h) 225 m pintopin measurement lowside power fet on resistance r dson(3l) 150 m pintopin measurement current limit threshold i th(ilim3) 1.7 2.2 2.55 a minimum on time t min_on3 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off3 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp3 pin ea transconductance g m3 310 470 620 s
ADP5051 preliminary technical data rev. prb | page 8 of 63 parameter symbol min typ max unit test conditions/c omments soft start soft start time t ss3 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup3 7 t ss3 ms c out discharge switch on resistance r dis3 250 channel 4 sync buck regulator fb4 pin fixed output options v out4 2.5 5.5 v fuse trim or i 2 c interface (5bit value) adjustable feedback voltage v fb4 0.800 v feedback voltage accuracy v fb4(default) ?0.55 +0.55 % t j = 25c ?1.25 +1.0 % 0c t j 85c ?1.5 +1.5 % ?40c t j +125c feedback bias current i fb4 0.1 a sw4 pin highside power fet on resistance r dson(4h) 225 m pintopin measurement lowside power fet on resistance r dson(4l) 150 m pintopin measurement current limit threshold i th(ilim4) 1.7 2.2 2.55 a minimum on time t min_on4 90 120 ns f sw = 250 khz to 1.4 mhz minimum off time t min_off4 1/9 t sw ns f sw = 250 khz to 1.4 mhz error amplifier (ea), comp4 pin ea transconductance g m4 310 470 620 s soft start soft start time t ss4 2.0 ms ss34 connected to vreg programmable soft start range 2.0 8.0 ms hiccup time t hiccup4 7 t ss4 ms c out discharge switch on resistance r dis4 250 supervisory specifications v in = 12 v, v vreg = 5.1 v; t j = ?40c to +125c for minimum and maximum specificatio ns, and t a = 25c for typical specifications, unless otherwise noted. table 4. parameter min typ max unit test conditions/comments threshold voltage (v th ) 0.494 0.500 0.505 v reset timeout period (t rp ) option 0 1.05 1.4 1.97 ms option 1 21 28 38 ms option 2 160 200 260 ms option 3 1.15 1.6 2.17 sec vcc to reset delay (t rd ) 80 s vth falling at 1 mv/s watchdog input watchdog timeout period (t wd ) option 0 4.8 6.3 8 ms option 1 79 102 135 ms option 2 1.14 1.6 2.15 sec option 3 25.6 sec wdi pulse width 80 ns wdi input threshold 0.4 1.2 v wdi input current (source) 8.5 14 18.5 a v wdi = v cc , time average
preliminary technical data ADP5051 rev. prb | page 9 of 63 parameter min typ max unit test conditions/comments wdi input current (sink) ?15 ?22 ?30 a v wdi = 0 v, time average manual reset input mr input pulse width 1 s mr glitch rejection 280 ns mr pullup resistance 32 55 80 k mr to reset delay 310 ns i 2 c interface timing specifications t a = 25c, v vdd = 3.3 v, v vddio = 3.3 v, unless otherwise noted. table 5. parameter min typ max unit description f scl 400 khz scl clock frequency t high 0.6 s scl high time t low 1.3 s scl low time t su, dat 100 ns data setup time t hd, dat 0 0.9 s data hold time 1 t su, sta 0.6 s setup time for a repeated start condition t hd, sta 0.6 s hold time for a start or repeated start c ondition t buf 1.3 s bus free time between a stop condition an d a start condition t su, sto 0.6 s setup time for a stop condition t r 20 + 0.1c b 2 300 ns rise time of scl and sda t f 20 + 0.1c b 2 300 ns fall time of scl and sda t sp 0 50 ns pulse width of suppressed spike c b 2 400 pf capacitive load for each bus line 1 a master device must provide a hold time of at lea st 300 ns for the sda signal (referred to the v ih minimum of the scl signal) to bridge the undefined region of the scl falling edge. 2 c b is the total capacitance of one bus line in picofa rads (pf). timing diagram s s p sr s = start condition sr = repeated start condition p = stop condition scl sda t hd,dat t su,dat t hd,sta t su,sta t su,sto t high t r t f t f t sp t r t low t buf 11635-102 figure 3. i 2 c interface timing diagram
ADP5051 preliminary technical data rev. prb | page 10 of 63 absolute maximum ratings table 6. parameter rating pvin1 to pgnd ?0.3 v to +18 v pvin2 to pgnd ?0.3 v to +18 v pvin3 to pgnd3 ?0.3 v to +18 v pvin4 to pgnd4 ?0.3 v to +18 v sw1 to pgnd ?0.3 v to +18 v sw2 to pgnd ?0.3 v to +18 v sw3 to pgnd3 ?0.3 v to +18 v sw4 to pgnd4 ?0.3 v to +18 v pgnd to gnd ?0.3 v to +0.3 v pgnd3 to gnd ?0.3 v to +0.3 v pgnd4 to gnd ?0.3 v to +0.3 v bst1 to sw1 ?0.3 v to +6.5 v bst2 to sw2 ?0.3 v to +6.5 v bst3 to sw3 ?0.3 v to +6.5 v bst4 to sw4 ?0.3 v to +6.5 v dl1 to pgnd ?0.3 v to +6.5 v dl2 to pgnd ?0.3 v to +6.5 v ss12, ss34 to gnd ?0.3 v to +6.5 v en1, en2, en3, en4 to gnd ?0.3 v to +6.5 v vreg to gnd ?0.3 v to +6.5 v sync/mode to gnd ?0.3 v to +6.5 v wdi, rsto , v th to gnd mr to gnd ?0.3 v to +6.5 v ?0.3 v to +3.6 v rt to gnd ?0.3 v to +3.6 v int , pwrgd to gnd ?0.3 v to +6.5 v fb1, fb2, fb3, fb4 to gnd 1 ?0.3 v to +3.6 v fb2 to gnd 2 ?0.3 v to +6.5 v fb4 to gnd 2 ?0.3 v to +7 v comp1, comp2, comp3, comp4 to gnd ?0.3 v to +3.6 v vdd, vddio to gnd ?0.3 v to +3.6 v scl, sda ?0.3 v to vddio + 0.3 v storage temperate range ?65c to +150c operational junction temperature range ?40c to +12 5c 1 this rating applies to the adjustable output volta ge models of the ADP5051 . 2 this rating applies to the fixed output voltage mo dels of the ADP5051 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera tional section of this specification is not implied. expos ure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worstcase conditions, that i s, a device soldered in a circuit board for surfacemount packa ges. table 7. thermal resistance package type ja jc unit 48lead lfcsp 27.87 2.99 c/w esd caution
preliminary technical data ADP5051 rev. prb | page 11 of 63 pin configuration and function descriptions 12 3 pvin1 pvin1 sw1 4 sw1 5 bst1 6 dl1 7 pgnd 2 4 p v i n 2 2 3 e n 2 2 2 c o m p 2 2 1 f b 2 2 0 p w r g d 1 9 s c l 1 8 s d a 1 7 v d d i o 1 6 f b 4 1 5 c o m p 4 1 4 e n 4 1 3 i n t 4 4 v r e g 4 5 f b 3 4 6 c o m p 3 4 7 s s 3 4 4 8 e n 3 4 3 s y n c / m o d e 4 2 v d d 4 1 r t 4 0 f b 1 3 9 c o m p 1 3 8 s s 1 2 3 7 e n 1 top view (not to scale) ADP5051 25 bst4 26 pgnd4 27 sw4 28 pvin4 29 rsto 30 mr 31 vth 32 wdi 33 pvin3 34 sw3 35 pgnd3 36 bst3 notes 1. the exposed pad must be connected and soldered to an external ground plane. 8 dl2 9 bst2 10 sw2 11 sw2 12 pvin2 11635-002 figure 4. pin configuration table 8. pin function descriptions pin no. mnemonic description 1 bst3 highside fet driver power supply for channe l 3. 2 pgnd3 power ground for channel 3. 3 sw3 switching node output for channel 3. 4 pvin3 power input for channel 3. connect a bypass capacitor between this pin and ground. 5 wdi watchdog refresh input from processor. 6 vth monitoring voltage threshold programming. 7 mr manual reset input, active low. 8 rsto opendrain reset output, active low. 9 pvin4 power input for channel 4. connect a bypass capacitor between this pin and ground. 10 sw4 switching node output for channel 4. 11 pgnd4 power ground for channel 4. 12 bst4 highside fet driver power supply for chann el 4. 13 int interrupt output on fault condition. opendrain out put port. 14 en4 enable input for channel 4. an external resi stor divider can be used to set the turnon thresho ld. 15 comp4 error amplifier output for channel 4. conn ect an rc network from this pin to ground. 16 fb4 feedback sensing input for channel 4. 17 vddio power supply for the i 2 c interface. 18 sda data input/output for the i 2 c interface. opendrain i/o port. 19 scl clock input for the i 2 c interface. 20 pwrgd powergood signal output. this opendrain output is the powergood signal for the selected ch annels. this pin can be programmed by the factory to set the i 2 c address of the part; the i 2 c address setting function replaces the powergood function on this pin. for more informati on, see the i2c addresses section. 21 fb2 feedback sensing input for channel 2. 22 comp2 error amplifier output for channel 2. conn ect an rc network from this pin to ground. 23 en2 enable input for channel 2. an external resi stor divider can be used to set the turnon thresho ld. 24, 25 pvin2 power input for channel 2. connect a b ypass capacitor between this pin and ground. 26, 27 sw2 switching node output for channel 2.
ADP5051 preliminary technical data rev. prb | page 12 of 63 pin no. mnemonic description 28 bst2 highside fet driver power supply for chann el 2. 29 dl2 lowside fet gate driver for channel 2. conn ect a resistor from this pin to ground to program t he current limit threshold for channel 2. 30 pgnd power ground for channel 1 and channel 2. 31 dl1 lowside fet gate driver for channel 1. conn ect a resistor from this pin to ground to program t he current limit threshold for channel 1. 32 bst1 highside fet driver power supply for chann el 1. 33, 34 sw1 switching node output for channel 1. 35, 36 pvin1 power input for the internal 5.1 v vre g linear regulator and the channel 1 buck regulator . connect a bypass capacitor between this pin and ground. 37 en1 enable input for channel 1. an external resi stor divider can be used to set the turnon thresho ld. 38 ss12 soft start time for channel 1 and channel 2 . connect a resistor divider from this pin to vreg and ground to configure the soft start time for channel 1 and cha nnel 2 (see the soft start section). this pin is al so used to configure parallel operation of channel 1 and chann el 2 (see the parallel operation section). 39 comp1 error amplifier output for channel 1. conn ect an rc network from this pin to ground. 40 fb1 feedback sensing input for channel 1. 41 rt connect a resistor from rt to ground to progr am the switching frequency from 250 khz to 1.4 mhz. for more information, see the oscillator section. 42 vdd output of the internal 3.3 v linear regulato r. connect a 1 f ceramic capacitor between this pi n and ground. 43 sync/mod e synchronization input/output (sync). to synchronize the switching frequency of the part to an external clock, connect this pin to an external clock with a freque ncy from 250 khz to 1.4 mhz. this pin can also be c onfigured as a synchronization output using the i 2 c interface or by factory fuse. forced pwm or automatic pwm/psm selection pin (mo de). when this pin is logic high, each channel oper ates in forced pwm or automatic pwm/psm mode, as specified by the psmx_on bits in register 6. when this pin is logic low, all channels operate in automatic pwm/psm mode , and the psmx_on settings in register 6 are ignore d. 44 vreg output of the internal 5.1 v linear regulat or. connect a 1 f ceramic capacitor between this p in and ground. 45 fb3 feedback sensing input for channel 3. 46 comp3 error amplifier output for channel 3. conn ect an rc network from this pin to ground. 47 ss34 soft start time for channel 3 and channel 4 . connect a resistor divider from this pin to vreg and ground to configure the soft start time for channel 3 and cha nnel 4 (see the soft start section). 48 en3 enable input for channel 3. an external resi stor divider can be used to set the turnon thresho ld. 0 epad exposed pad (analog ground). the exposed pad must be connected and soldered to an external grou nd plane.
preliminary technical data ADP5051 rev. prb | page 13 of 63 typical performance characteristics 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v 11635-003 figure 5. channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 11635-004 figure 6. channel 1/channel 2 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 efficienc y (%) i out (a) f sw = 1.0mhz f sw = 600khz f sw = 300khz 11635-005 figure 7. channel 1/channel 2 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficiency (%) i out (a) v out = 1.2v, fpwm v out = 1.2v, auto pwm/psm v out = 1.8v, fpwm v out = 1.8v, auto pwm/psm v out = 3.3v, fpwm v out = 3.3v, auto pwm/psm 11635-006 figure 8. channel 1/channel 2 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and automatic pwm/psm modes 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5.0v 11635-007 figure 9. channel 3/channel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 11635-008 figure 10. channel 3/channel 4 efficiency curve, v in = 5.0 v, f sw = 600 khz, fpwm mode
ADP5051 preliminary technical data rev. prb | page 14 of 63 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1.0 1.2 efficienc y (%) i out (a) f sw = 1.0mhz f sw = 600khz f sw = 300khz 11635-009 figure 11. channel 3/channel 4 efficiency curve, v in = 12 v, v out = 1.8 v, fpwm mode 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 2 efficiency (%) i out (a) v out = 1.2v, fpwm v out = 1.2v, auto pwm/psm v out = 1.8v, fpwm v out = 1.8v, auto pwm/psm v out = 3.3v, fpwm v out = 3.3v, auto pwm/psm 11635-010 figure 12. channel 3/channel 4 efficiency curve, v in = 12 v, f sw = 600 khz, fpwm and and automatic pwm/psm modes ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 1 2 3 4 load regul a tion (%) i out (a) 11635-011 figure 13. channel 1 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input voltage (v) 11635-012 figure 14. channel 1 line regulation, v out = 3.3 v, i out = 4 a, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 0.2 0.4 0.6 0.8 1.0 1.2 load regul a tion (%) i out (a) 11635-013 figure 15. channel 3 load regulation, v in = 12 v, v out = 3.3 v, f sw = 600 khz, fpwm mode ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 4.5 6.0 7.5 9.0 10.5 12.0 13.5 15.0 line regul a tion (%) input voltage (v) 11635-014 figure 16. channel 3 line regulation, v out = 3.3 v, i out = 1 a, f sw = 600 khz, fpwm mode
preliminary technical data ADP5051 rev. prb | page 15 of 63 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?50 ?20 10 40 70 100 130 feedback vo lt age accurac y (%) temperature (c) 11635-015 figure 17. 0.8 v feedback voltage accuracy vs. temp erature for channel 1, adjustable output model ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 5 10 15 20 25 30 35 output vo lt age error (%) vid code vid1 vid2 vid3 vid4 11635-016 figure 18. output voltage error vs. vid code, adjus table output model 550 600 650 700 750 800 850 ?50 ?20 10 40 70 100 130 frequenc y (khz) temperature (c) 11635-017 figure 19. frequency vs. temperature, v in = 12 v 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ?50 0 25 ?25 50 75 125 100 150 quiescent current (ma) temperature (c) 11635-018 figure 20. quescient current vs. temperature (inclu des pvin1, pvin2, pvin3, and pvin4) 15 25 35 45 55 65 75 shutdown current (a) temperature (c) ?50 0 25 ?25 50 75 125 100 150 v in = 4.5v v in = 7.0v v in = 12v v in = 15v 11635-019 figure 21. shutdown current vs. temperature (en1, e n2, en3, and en4 low) 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 ?50 ?20 10 40 70 100 130 uvlo threshold (v) temperature (c) rising falling 11635-020 figure 22. uvlo threshold vs. temperature
ADP5051 preliminary technical data rev. prb | page 16 of 63 0 1 2 3 4 5 6 7 4 6 8 10 12 14 16 current limit (a) input voltage (v) r ilim = 22k r ilim = open r ilim = 47k 11635-021 figure 23. channel 1/channel 2 current limit vs. in put voltage 0 20 40 60 80 100 120 140 160 180 200 ?50 ?20 10 40 70 100 130 minimum on time (ns) temperature (c) ch1/ch2 ch3/ch4 11635-022 figure 24. minimum on time vs. temperature ch1 5.00v ch2 10.0mv b w m1.00s a ch1 7.40v 2 1 v out sw 11635-028 figure 25. steady state waveform at heavy load, v in = 12 v, v out = 3.3 v, i out = 3 a, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, fpwm mode ch1 5.00v ch2 50.0mv b w m100s a ch1 11.0mv 2 1 v out sw 11635-029 figure 26. steady state waveform at light load, v in = 12 v, v out = 3.3 v, i out = 30 ma, f sw = 600 khz, l = 4.7 h, c out = 47 f 2, automatic pwm/psm mode ch1 50.0mv b w ch4 2.00a m100s a ch1 ?22.0mv 1 4 v out i out 11635-030 figure 27. channel 1/channel 2 load transient, 1 a to 4 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 2.2 h, c out = 47 f 2 ch3 2.00a b w ch4 2.00a b w ch2 100mv b w m100s a ch2 ?56.0mv 2 4 v out i out2 i out1 11635-031 figure 28. load transient, channel 1/channel 2 para llel output, 0 a to 6 a, v in = 12 v, v out = 3.3 v, f sw = 600 khz, l = 4.7 h, c out = 47 f 4
preliminary technical data ADP5051 rev. prb | page 17 of 63 ch1 500mv b w ch2 5.00v ch3 5.00v b w ch4 2.00a m1.00ms a ch1 650mv 1 3 2 4 v out i out en pwrgd 11635-032 figure 29. channel 1/channel 2 soft start with 4 a resistance load, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch3 1.00v b w ch1 10.0v b w ch4 1.00a b w ch2 5.00v b w m400s a ch2 2.80v 1 4 2 3 v in v out en i out 11635-033 figure 30. startup with precharged output, v in = 12 v, v out = 3.3 v ch3 5.00v b w ch1 500mv b w ch4 5.00a b w ch2 5.00v b w m10.0ms a ch1 650mv 1 4 2 3 v out i out en pwrgd 11635-034 figure 31. channel 1/channel 2 shutdown with active output discharge, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch1 500mv b w ch4 5.00a ch2 10.00v b w m10.0ms a ch1 970mv 1 4 2 v out i out sw 11635-135 figure 32. short-circuit protection entry, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch1 500mv b w ch4 5.00a b w ch2 10.0v b w m10.0ms a ch1 970mv 1 4 2 v out i out sw 11635-136 figure 33. short-circuit protection recovery, v in = 12 v, v out = 1.2 v, f sw = 600 khz, l = 1 h, c out = 47 f 2 ch2 200mv b w m200s a ch2 1.21v 2 v out 11635-137 figure 34. channel 1 dynamic voltage scaling (dvs) from 1.1 v to 1.3 v, 62.5 s interval, v in = 12 v, i out = 4 a, f sw = 600 khz, l = 1 h, c out = 47 f 2
ADP5051 preliminary technical data rev. prb | page 18 of 63 ch2 200mv b w m200s a ch2 1.18v 2 v out 11635-138 figure 35. channel 1 dynamic voltage scaling (dvs) from 1.3 v to 1.1 v, 62.5 s interval, v in = 12 v, i out = 4 a, f sw = 600 khz, l = 1 h, c out = 47 f 2
preliminary technical data ADP5051 rev. prb | page 19 of 63 theory of operation the ADP5051 is a micropower management unit that combines four high performance buck regulators and a supervi sory circuit with a voltage monitor, watchdog, and manual reset in a 48lead lfcsp package to meet demanding performance and boa rd space requirements. the device enables direct conne ction to high input voltages up to 15 v with no preregulators to make applications simpler and more efficient. buck regulator operational modes pulse-width modulation (pwm) mode in pwm mode, the buck regulators in the ADP5051 operate at a fixed frequency; this frequency is set by an intern al oscillator that is programmed by the rt pin. at the start of e ach oscillator cycle, the highside mosfet turns on and sends a po sitive voltage across the inductor. the inductor current increases until the current sense signal exceeds the peak inductor curr ent threshold that turns off the highside mosfet; this threshold is set by the error amplifier output. during the highside mosfet off time, the inductor current decreases through the lowside mosfet until the nex t oscillator clock pulse starts a new cycle. the buck regulators in the ADP5051 regulate the output voltage by adjusting the peak i nductor current threshold. power save mode (psm) mode to achieve higher efficiency, the buck regulators i n the ADP5051 smoothly transition to variable frequency psm opera tion when the output load falls below the psm current thresho ld. when the output voltage falls below regulation, the buck regulator enters pwm mode for a few oscillator cycles until t he voltage increases to within regulation. during the idle tim e between bursts, the mosfet turns off, and the output capaci tor supplies all the output current. the psm comparator monitors the internal compensati on node, which represents the peak inductor current in formation. the average psm current threshold depends on the in put voltage (v in ), the output voltage (v out ), the inductor, and the output capacitor. because the output voltage occasi onally falls below regulation and then recovers, the output volt age ripple in psm operation is larger than the ripple in the forc ed pwm mode of operation under light load conditions. forced pwm and automatic pwm/psm modes the buck regulators can be configured to always ope rate in pwm mode using the sync/mode pin and the i 2 c interface. in forced pwm (fpwm) mode, the regulator continues to operate at a fixed frequency even when the output c urrent is below the pwm/psm threshold. in pwm mode, efficienc y is lower when compared to psm mode under light load conditions. the lowside mosfet remains on when the inductor current falls to less than 0 a, causing th e ADP5051 to enter continuous conduction mode (ccm). the buck regulators can be configured to operate in automatic pwm/psm mode using the sync/mode pin and the i 2 c interface. in automatic pwm/psm mode, the buck regu lators operate in either pwm mode or psm mode, depending o n the output current. when the average output current fal ls below the pwm/psm threshold, the buck regulator enters psm mo de operation; in psm mode, the regulator operates with a reduced switching frequency to maintain high efficiency. th e lowside mosfet turns off when the output current reaches 0 a, causing the regulator to operate in discontinuous mode (dcm ). the user can alternate between forced pwm (fpwm) mo de and automatic pwm/psm mode during operation. the fl exible configuration capability during operation of the de vice enables efficient power management. when a logic high level is applied to the sync/mode pin (or when sync/mode is configured as a clock input or ou tput), the operational mode of each channel is set by the psmx_on bit in register 6. when the psmx_on bit is set to 0 , it configures the channel for forced pwm mode, and when the psmx_ on bit is set to 1, it configures the channel for automatic p wm/psm mode. when a logic low level is applied to the sync/mode pin, the operational mode of all four buck regulators is automatic pwm/psm mode, and the settings of the psmx_on bits in register 6 are ignored. table 9 describes the function of the sync/mode pin in setting the operational mode of the device. table 9. configuring the mode of operation using th e sync/mode pin sync/mode pin mode of operation for each channel high specified by the psmx_on bit setting in register 6 (0 = forced pwm mode; 1 = automatic pwm/psm mode) clock input/output specified by the psmx_on bit set ting in register 6 (0 = forced pwm mode; 1 = automatic pwm/psm mode) low automatic pwm/psm mode (psmx_on bit settings in register 6 are ignored) for example, with the sync/mode pin high, write 1 t o the psm4_on bit in register 6 to configure automatic pwm/ psm mode operation for channel 4, and write 0 to the psm 1_on, psm2_on, and psm3_on bits to configure forced pwm m ode for channel 1, channel 2, and channel 3.
ADP5051 preliminary technical data rev. prb | page 20 of 63 adjustable and fixed output voltages the ADP5051 provides adjustable and fixed output voltage settings via the i 2 c interface or factory fuse. for the adjustable output settings, use an external resistor divider t o set the desired output voltage via the feedback reference v oltage (0.8 v for channel 1 to channel 4). for the fixed output settings, the feedback resisto r divider is built into the ADP5051 , and the feedback pin (fbx) must be tied directly to the output. each buck regulator ch annel can be programmed for a specific output voltage range usin g the vidx bits in register 2 to register 4. table 10 lists the f ixed output voltage ranges configured by the vidx bits. table 10. fixed output voltage ranges set by the vi dx bits channel fixed output voltage range set by the vidx bits channel 1 0.85 v to 1.6 v in 25 mv steps channel 2 3.3 v to 5.0 v in 300 mv or 200 mv steps channel 3 1.2 v to 1.8 v in 100 mv steps channel 4 2.5 v to 5.5 v in 100 mv steps the output range can also be programmed by factory fuse. if a different output voltage range is required, conta ct your local analog devices, inc., sales or distribution represe ntative. dynamic voltage scaling (dvs) the ADP5051 provides a dynamic voltage scaling (dvs) function for channel 1 and channel 4; these outputs can be pr ogrammed in realtime via the i 2 c interface (register 5, dvs_cfg). the dvs_cfg register is used to enable dvs and to set t he step interval during the transition (see table 29). it is recommended that the user enable the dvs func tion before setting the output voltage for channel 1 or c hannel 4. (the output voltage for channel 1 is set using the vid1 bits in register 2; the output voltage for channel 4 is set using the vid4 bits in register 4.) enabling dvs after setting the vid value rapidly changes the output voltage to the nex t target voltage, which can result in problems such as a pwrgd failur e, an overvoltage protection (ovp) event, or an overcurre nt protection (ocp) event. figure 36 shows the dynamic voltage sca ling function. output new vid code old vid code old vid new vid vidx vid for ch1 or ch4 dvsx_intval setting 25mv for ch1 (100mv for ch4) 11635-035 figure 36. dynamic voltage scaling during the dvs transition period, the regulator is forced into pwm operation, and ovp latchoff, scp latchoff, an d hiccup protection are masked. internal regulators (vreg and vdd) the internal vreg regulator in the ADP5051 provides a stable 5.1 v power supply for the bias voltage of the mosfe t drivers. the internal vdd regulator in the ADP5051 provides a stable 3.3 v power supply for internal control circuits. c onnect a 1.0 f ceramic capacitor between vreg and ground, and conn ect another 1.0 f ceramic capacitor between vdd and gro und. the internal vreg and vdd regulators are active as long as pvin1 is available. the internal vreg regulator can provide a total loa d of 95 ma including the mosfet driving current, and it can be used as an always alive 5.1 v power supply for a small syste m current demand. the current limit circuit is included in th e vreg regulator to protect the circuit when the part is h eavily loaded. the vdd regulator is for internal circuit use and i s not recom mended for other purposes. separate supply applications the ADP5051 supports separate input voltages for the four buck regulators. this means that the input voltages for the four buck regulators can be connected to different supply vol tages. the pvin1 voltage provides the power supply for the internal regulators and the control circuitry. therefore, if the user plans to use separate supply voltages for the buck regula tors, the pvin1 voltage must be above the uvlo threshold before the other channels begin to operate. precision enabling can be used to monitor the pvin1 voltage and to delay the startup of the outputs to ensure t hat pvin1 is high enough to support the outputs in regulation. f or more information, see the precision enabling section. the ADP5051 supports cascading supply operation for the four buck regulators. as shown in figure 37, pvin2, pvin3, and pvin4 are powered from the channel 1 output. in thi s config uration, the channel 1 output voltage must be highe r than the uvlo threshold for pvin2, pvin3, and pvin4. pvin1 buck 1 buck 2 v out1 pvin2 to pvin4 v out2 to v out4 v in 11635-036 figure 37. cascading supply application lowside device selection the buck regulators in channel 1 and channel 2 integ rate 4 a highside power mosfet and lowside mosfet drivers. the
preliminary technical data ADP5051 rev. prb | page 21 of 63 nchannel mosfets selected for use with the ADP5051 must be able to work with the synchronized buck regulators. in general, a low r dson nchannel mosfet can be used to achieve higher efficiency; dual mosfets in one package (for both c hannel 1 and channel 2) are recommended to save space on the printed circuit board (pcb). for more information, see the lowside power device selection section. bootstrap circuitry each buck regulator in the ADP5051 has an integrated bootstrap regulator. the bootstrap regulator requires a 0.1 f ceramic capacitor (x5r or x7r) between the bstx and swx pins to provide the gate drive voltage for the highside mo sfet. active output discharge switch each buck regulator in the ADP5051 integrates a discharge switch from the switching node to ground. this swit ch is turned on when its associated regulator is disabled, which helps to discharge the output capacitor quickly. the typical value of the discharge switch is 250 for channel 1 to channel 4. the discharge switch function can be enabled or dis abled for each channel by factory fuse or by using the i 2 c interface (register 6, opt_cfg). precision enabling the ADP5051 has an enable control pin for each regulator, including the ldo regulator. the enable control pin (enx) features a precision enable circuit with a 0.8 v refe rence voltage. when the voltage at the enx pin is greater than 0.8 v, the regulator is enabled. when the voltage at the enx pin less th an 0.725 v, the regulator is disabled. an internal 1 m pulldo wn resistor prevents errors if the enx pin is left floating. the precision enable threshold voltage allows easy sequencing of channels within the part, as well as sequencing between the ADP5051 and other input/output supplies. the enx pin can a lso be used as a programmable uvlo input using a resist or divider (see figure 38). for more information, see the prog ramming the uvlo input section. 0.8v deglitch timer internal enable enx r1 r2 1m input/output voltage ADP5051 11635-037 figure 38. precision enable diagram for one channel in addition to the enx pins, the i 2 c interface (register 1, pctrl) can also be used to enable and disable each channel. the on/off status of a channel is controlled by the i 2 c enable bit for the channel (register 1, chx_on[3:0]) and the exter nal hardware enable pin (enx) for the channel (logical and). the default value of the i 2 c enable bit (chx_on = 1) specifies that the channel enable is controlled by the extern al hardware enable pin (enx). pulling the external enx pin low resets the channel and forces the corresponding chx_on bit to the default value (1) to support another startup when the exter nal enx pin is pulled high again. oscillator the switching frequency (f sw ) of the ADP5051 can be set to a value from 250 khz to 1.4 mhz by connecting a resistor from the rt pin to ground. the value of the rt resistor can be calculated as follows: r rt (k) = [14,822/ f sw (khz)] 1.081 figure 39 shows the typical relationship between the switching frequency (f sw ) and the rt resistor. the adjustable frequency allows users to make decisions based on the tradeo ff between efficiency and solution size. 1.6m 1.4m 1.2m 1.0m 800k frequenc y (hz) 600k 400k 200k 0 0 20 40 rt resistor (k ) 60 80 11635-044 figure 39. switching frequency vs. rt resistor for channel 1 and channel 3, the frequency can be se t to half the master switching frequency set by the rt pin. t his setting is configured using register 8 (bit 7 for channel 3, and bit 6 for channel 1). if the master switching frequency is le ss than 250 khz, this halving of the frequency for channel 1 or chan nel 3 is not recommended. phase shift by default, the phase shift between channel 1 and ch annel 2 and between channel 3 and channel 4 is 180 (see figure 40) . this
ADP5051 preliminary technical data rev. prb | page 22 of 63 value provides the benefits of outofphase operati on by reducing the input ripple current and lowering the ground no ise. ch2 ch1 (? f sw optional) ch4 sw 180 phase shift 0 reference 90 phase shift 270 phase shift 0, 90,180, or 270 adjustable ch3 (? f sw optional) 11635-040 figure 40. phase shift diagram, four buck regulator s for channel 2 to channel 4, the phase shift with res pect to channel 1 can be set to 0, 90, 180, or 270 using reg ister 8, sw_cfg (see figure 41). when parallel operation of channel 1 and channel 2 is configured, the switching frequenc y of channel 2 is locked to a 180 phase shift with respect to chann el 1. ch3 10.0v b w ch1 10.0v b w ch4 10.0v b w ch2 10.0v b w m400ns a ch1 7.40v 1 2 3 4 sw1 sw2 sw3 sw4 11635-146 figure 41. i 2 c configurable 90 phase shift waveforms, four buck regulators synchronization input/output the switching frequency of the adp505 1 can be synchronized to an external clock with a frequency range from 250 khz to 1.4 mhz. the adp505 1 automatically detects the presence of an external clock applied to the sync/mode pin, and the switching frequency transitions smoothly to the fre quency of the external clock. when the external clock signal stops, the device automatically switches back to the internal clock and continues to operate. note that the internal switching frequency set by t he rt pin must be programmed to a value that is close to the external clock value for successful synchronization; the sug gested frequency difference is less than 15% in typical app lications. the sync/mode pin can be configured as a synchroniz ation clock output by factory fuse or via the i 2 c interface (register 10, hiccup_cfg). a positive clock pulse with a 50% duty c ycle is generated at the sync/mode pin with a frequency equ al to the internal switching frequency set by the rt pin. the re is a short delay time (approximately 15% of t sw ) from the generated synchronization clock to the channel 1 switching no de. figure 42 shows two ADP5051 s configured for frequency synchronization mode: one ADP5051 device is configured as the clock output to synchronize another ADP5051 device. it is recommended that a 100 k pullup resistor be used to prevent logic errors when the sync/mode pin is left floatin g. ADP5051 100k vreg sync/mode sync/mode ADP5051 11635-039 figure 42. two ADP5051 devices configured for synchronization mode in the configuration shown in figure 42, the phase shift between channel 1 of the first ADP5051 device and channel 1 of the second ADP5051 device is 0 (see figure 43). ch3 5.00v b w ch1 2.00v b w ch2 5.00v b w m400ns a ch1 560mv 1 2 3 sw1 at first ADP5051 sw1 at second ADP5051 sync-out at first ADP5051 11635-148 figure 43. waveforms of two ADP5051 devices operating in synchronization mode soft start the buck regulators in the ADP5051 include soft start circuitry that ramps the output voltage in a controlled manne r during startup, thereby limiting the inrush current. the s oft start time is typically fixed at 2 ms for each buck regulator when the ss12 and ss34 pins are tied to vreg. to set the soft start time to a value of 2 ms, 4 ms , or 8 ms, connect a resistor divider from the ss12 or ss34 pin to the vr eg pin and ground (see figure 44). this configuration may be re quired to accommodate a specific startup sequence or an appl ication with a large output capacitor.
preliminary technical data ADP5051 rev. prb | page 23 of 63 level detector and decoder vreg top resistor bottom resistor ss12 or ss34 ADP5051 11635-041 figure 44. level detector circuit for soft start use the ss12 pin to program the soft start time and parallel operation for channel 1 and channel 2. use the ss34 pin to prog ram the soft start time for channel 3 and channel 4. table 11 provides the values of the resistors needed to set the soft star t time. table 11. soft start time set by the ss12 and ss34 pins soft start time r top (k) r bot (k) channel 1 channel 2 channel 3 channel 4 0 n/a 1 2 ms 2 ms 2 ms 2 ms 100 600 2 ms parallel 2 ms 4 ms 200 500 2 ms 8 ms 2 ms 8 ms 300 400 4 ms 2 ms 4 ms 2 ms 400 300 4 ms 4 ms 4 ms 4 ms 500 200 8 ms 2 ms 4 ms 8 ms 600 100 8 ms parallel 8 ms 2 ms n/a 1 0 8 ms 8 ms 8 ms 8 ms 1 n/a = not applicable. parallel operation the ADP5051 supports twophase parallel operation of channel 1 and channel 2 to provide a single output with up to 8 a of current. take the following steps to configure chan nel 1 and channel 2 as a twophase single output in parallel operation (see figure 45): ? use the ss12 pin to select parallel operation as spe cified in table 11. ? leave the comp2 pin open. ? use the fb1 pin to set the output voltage. ? connect the fb2 pin to ground (fb2 is ignored). ? connect the en2 pin to ground (en2 is ignored). channel 1 buck regulator (4a) channel 2 buck regulator (4a) fb1 pvin1 v out (up to 8a) v in en1 en2 comp1 ss12 sw1 l1 fb2 sw2 l2 pvin2 comp2 vreg 11635-042 figure 45. parallel operation for channel 1 and cha nnel 2 when operating channel 1 and channel 2 in the paral lel configuration, configure the channels as follows: ? set the input voltages and current limit settings f or channel 1 and channel 2 to the same values. ? operate both channels in forced pwm mode. bits pertaining to channel 2 in the configuration r egisters cannot be used. these bits include ch2_on in registe r 1, vid2 in register 3, ovp2_on and scp2_on in register 7, phase2 in register 8, and pwrg2 in register 13. current balance in parallel configuration is well r egulated by the internal control loop. figure 46 shows the typic al current balance matching in the parallel output configurati on. 0 1 2 3 4 5 6 0 2 4 6 8 10 channe l current (a) total output load (a) ch1 ch2 ideal 11635-151 figure 46. current balance in parallel output confi guration, v in = 12 v, v out = 1.2 v, f sw = 600 khz, fpwm mode startup with precharged output the buck regulators in the ADP5051 include a precharged startup feature to protect the lowside mosfets from damage during startup. if the output voltage is precharged before the regulator is turned on, the regulator prevents the reverse induc tor current, which discharges the output capacitor, until the in ternal soft
ADP5051 preliminary technical data rev. prb | page 24 of 63 start reference voltage exceeds the precharged volt age on the feedback (fbx) pin. current limit protection the buck regulators in the ADP5051 include peak current limit protection circuitry to limit the amount of positiv e current flowing through the highside mosfet. the peak current limi t on the power switch limits the amount of current that can flow from the input to the output. the programmable current limit threshold feature allows for the use of small size inductors for low current applications. to configure the current limit threshold for channe l 1, connect a resistor from the dl1 pin to ground. to configure the current limit threshold for channel 2, connect another resis tor from the dl2 pin to ground. table 12 lists the peak current l imit threshold settings for channel 1 and channel 2. table 12. peak current limit threshold settings for channel 1 and channel 2 r ilim1 or r ilim2 typical peak current limit threshold (a) floating 4.4 47 k 2.63 22 k 6.44 the buck regulators in the ADP5051 include negative current limit protection circuitry to limit certain amounts of negative current flowing through the lowside mosfet. frequency foldback the buck regulators in the ADP5051 include frequency fold back to prevent output current runaway when a hard short occurs on the output. frequency foldback is impleme nted as follows: ? if the voltage at the fbx pin falls below half the target output voltage, the switching frequency is reduced by half. ? if the voltage at the fbx pin falls again to below onefourth the target output voltage, the switching frequency is reduced to half its current value, that is, to onefourth o f f sw . the reduced switching frequency allows more time fo r the inductor current to decrease but also increases the ripple current during peak current regulation. this results in a r eduction in average current and prevents output current runaway . pulse skip mode under maximum duty cycle under maximum duty cycle conditions, frequency fold back maintains the output in regulation. if the maximum duty cycle is reached, for example, when the input voltage dec reases, the pwm modulator skips every other pwm pulse, resultin g in a switching frequency foldback of onehalf. if the du ty cycle increases further, the pwm modulator skips two of every three pwm pulses, resulting in a switching frequency foldback to one third of the switching frequency. frequency foldback increases t he effective maximum duty cycle, thereby decreasing the dropout voltage between the input and output voltages. hiccup protection the buck regulators in the ADP5051 include a hiccup mode for ocp. when the peak inductor current reaches the cur rent limit threshold, the highside mosfet turns off and the l owside mosfet turns on until the next cycle. when hiccup mode is active, the overcurrent fault c ounter is incremented. if the overcurrent fault counter reach es 15 and overflows (indicating a shortcircuit condition), b oth the high side and lowside mosfets are turned off. the buck regulator remains in hiccup mode for a period equal to seven soft start cycles and then attempts to restart from soft start . if the short circuit fault has cleared, the regulator resumes no rmal operation; otherwise, it reenters hiccup mode after the soft s tart. hiccup protection is masked during the initial soft start cycle to enable startup of the buck regulator under heavy lo ad conditions. note that careful design and proper component selec tion are required to ensure that the buck regulator recovers from hiccup mode under heavy loads. the hiccupx_off bits in reg ister 10 can be used to disable hiccup protection for each b uck regulator. when hiccup protection is disabled, the frequency f oldback feature is still available for overcurrent protection. latchoff protection the buck regulators in the ADP5051 have an optional latchoff mode to protect the device from serious problems su ch as short circuit and overvoltage conditions. latchoff mode can be enabled via the i 2 c interface or by factory fuse. short-circuit latch-off mode shortcircuit latchoff mode is enabled by factory fuse or by writing 1 to the scpx_on bit in register 7, lch_cfg. when sho rt circuit latchoff mode is enabled and the protectio n circuit detects an overcurrent status after a soft start, t he buck regulator enters hiccup mode and attempts to restart. if seve n continuous restart attempts are made and the regulator remains in the fault condition, the regulator is shut down. this shutdow n (latchoff) condition is cleared only by reenabling the channel or by resetting the channel power supply. figure 47 shows the short circuit latch off detection function.
preliminary technical data ADP5051 rev. prb | page 25 of 63 output voltage time latch-off chx_lch latch off this regulator short circuit detected by counter overflow pwrgd 7 t ss scp latch-off function enabled after 7 restart attempts write 1 to chx_lch bit attempt to restart 11635-045 figure 47. short-circuit latch-off detection the shortcircuit latchoff status can be read from register 12, lch_status. to clear the status bit, write 1 to the bit (if the fault no longer persists). the status bit is latched unti l 1 is written to the bit or the part is reset by the internal vdd po weron reset signal. note that shortcircuit latchoff mode does not work if hiccup protection is disabled. overvoltage latch-off mode overvoltage latchoff mode is enabled by factory fu se or by writing 1 to the ovpx_on bit in register 7, lch_cfg. the overvoltage latchoff threshold is 124% of the nominal output voltage level. when the output voltage exceeds this threshold, the protection circuit detects the overvoltage stat us and the regu lator shuts down. this shutdown (latchoff) conditi on is cleared only by reenabling the channel or by resetting the channel power supply. figure 48 shows the overvoltage latch off detection function. output voltage time latch off this regulator latch-off chx_lch write 1 to chx_lch bit 124% nominal output 100% nominal output chx on 11635-046 figure 48. overvoltage latch-off detection the overvoltage latchoff status can be read from r egister 12, lch_status. to clear the status bit, write 1 to the bit (if the fault no longer persists). the status bit is latched unti l 1 is written to the bit or the part is reset by the internal vdd power on reset signal. undervoltage lockout (uvlo) undervoltage lockout circuitry monitors the input v oltage level of each buck regulator in the ADP5051 . if any input voltage (pvinx pin) falls below 3.78 v (typical), the corresp onding channel is turned off. after the input voltage rise s above 4.2 v (typical), the soft start period is initiated, and the corresponding channel is enabled when the enx pin is high. note that a uvlo condition on channel 1 (pvin1 pin) has a higher priority than a uvlo condition on other ch annels, which means that the pvin1 supply must be available before other channels can be operated. powergood function the ADP5051 includes an opendrain powergood output (pwrgd pin) that becomes active high when the selec ted buck regulators are operating normally. by default, the pwrgd pin monitors the output voltage on channel 1. other chan nels can be configured to control the pwrgd pin when the ADP5051 is ordered (see table 59). the powergood status of each channel (pwrgx bit) c an be read back via the i 2 c interface (register 13, status_rd). a value of 1 for the pwrgx bit indicates that the reg ulated output voltage of the buck regulator is above 90.5% (typic al) of its nominal output. when the regulated output voltage of the bu ck regulator falls below 87.2% (typical) of its nominal output for a delay time greater than approximately 50 s, the pwrgx bit is s et to 0. the output of the pwrgd pin is the logical and of t he internal unmasked pwrgx signals. an internal pwrgx signal mu st be high for a validation time of 1 ms before the pwrgd pin goes high; if one pwrgx signal fails, the pwrgd pin goes low with no delay. the channels that control the pwrgd pin (cha nnel 1 to channel 4) are specified by factory fuse or by setti ng the appro priate bits in register 11 (pwrgd_mask) via the i 2 c interface. interrupt function the ADP5051 provides an interrupt output ( int pin) for fault conditions. during normal operation, the int pin is pulled high (use an external pullup resistor). when a fault co ndition occurs, the ADP5051 pulls the int pin low to alert the i 2 c host processor that a fault condition has occurred. six interrupt sources can trigger the int pin. by default, no interrupt sources are configured. to select one or more interrupt sources to trigger the int pin, set the appropriate bits to 1 in register 15, int_mask (see table 49). when the int pin is triggered, one or more bits in register 14 (bits[5:0]) are set to 1. the fault condition that triggered the int pin can be read from register 14, int_status (see tab le 13). table 13. fault conditions for device interrupt (re gister 14) interrupt description
ADP5051 preliminary technical data rev. prb | page 26 of 63 interrupt description temp_int junction temperature has exceeded the con figured threshold (selected in register 9) lvin_int pvin1 voltage has fallen below the configu red threshold (selected in register 9) pwrg4_int powergood failure detected on channel 4 pwrg3_int powergood failure detected on channel 3 pwrg2_int powergood failure detected on channel 2 pwrg1_int powergood failure detected on channel 1 to clear an interrupt, write 1 to the appropriate b it in register 14 (int_status), take all enx pins low, or reset the p art using the internal vdd poweron reset signal. reading the int errupt or writing 0 to the bit does not clear the interrupt. thermal shutdown if the ADP5051 junction temperature exceeds 150 c, the thermal shutdown (tsd) circuit turns off the ic except for the internal linear regulators. extreme junction temperatures ca n be the result of high current operation, poor circuit boar d design, or high ambient temperature. a 15 c hysteresis is included so that the ADP5051 does not return to operation after thermal shutdow n until the onchip temperature falls below 135 c. when the part exits thermal shutdown, a soft start is initiated f or each enabled channel. the thermal shutdown status can be read via the i 2 c interface (register 12, lch_status). when thermal shutdown is detected, the tsd_lch bit (bit 4) is set to 1. to clear the s tatus bit, write 1 to the bit (if the fault no longer persists). the s tatus bit is latched until 1 is written to the bit or the part is reset by the internal vdd poweron reset signal. overheat detection in addition to thermal shutdown protection, the ADP5051 provides an overheat warning function that compares the junction temperature with the specified overheat th reshold: 105, 115, or 125. the overheat threshold is configured in register 9, th_cfg. unlike thermal shutdown, the ove rheat detection function sends a warning signal but does not shut down the part. when the junction temperature exceed s the overheat threshold, the status bit temp_int in regi ster 14 is set to 1. the status bit is latched until 1 is writ ten to the bit, all enx pins are taken low, or the part is reset by the internal vdd poweron reset signal. the overheat detection function can be used to send a warning signal to the host processor. after the host proces sor detects the overheat warning signal, the processor can take act ion to prepare for a possible impending thermal shutdown. figure 49 shows the overheat warning function. junction temperature time temp_int (heat status) overheat condition detected normal temperature 115c (adjustable) 11635-047 figure 49. overheat warning function low input voltage detection in addition to under voltage lockout (uvlo), the ADP5051 provides a low input voltage detection circuit to m onitor pvin1; this circuit compares the input voltage with the sp ecified voltage threshold. the voltage threshold can be set from 4.2 v to 11.2 v in steps of 0.5 v using register 9, th_cfg. unlike uvlo shutdown, the low input voltage detection function sends a warning signal but does not shut down the part. whe n the pvin1 input voltage falls below the threshold, the status bit lvin_int in register 14 is set to 1. the status bit is latche d until 1 is written to the bit, all enx pins are taken low, or the part is reset by the internal vdd poweron reset signal. the low input voltage detection function can be use d to send a warning signal to the host processor. after the hos t processor detects the low input voltage warning signal, the p rocessor can take action to prepare for a possible impending uvl o shutdown. figure 50 shows the low input voltage warning functi on. input voltage on pvin1 time lvin_int (lvin status) low input voltage condition detected 12v input voltage 10.7v (adjustable) 11635-048 figure 50. low input voltage warning function (v in = 12 v) supervisory the ADP5051 provides microprocessor supply voltage super vision by controlling the reset input of the microp rocessor. code execution errors are avoided during powerup, power down, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by a llowing supply voltage stabilization with a fixed timeout reset pu lse after the supply voltage rises above the threshold. in additi on, problems with microprocessor code execution can be monitored with a
preliminary technical data ADP5051 rev. prb | page 27 of 63 watchdog timer. note that the supervisory circuitry only activates when one of the enx pins of the four buck regulator s is high. reset output the ADP5051 has an activelow, opendrain reset output. this output structure requires an external pullup resis tor to connect the reset output to a voltage rail no higher than 6 v. the resistor must comply with the logic low and logic high voltage le vel requirements of the microprocessor while also supplying input cu rrent and leakage paths on the rsto pin. a 10 k resistor is adequate in most situations. the reset output asserts when the monitored rail is below the threshold (v th ) and when wdi is not serviced within the watchdog timeout period (t wd ). reset remains asserted for the duration of the reset active timeout period (t rp ) after v cc rises above the reset threshold or after the watchdog tim er times out. there are four options for the reset active timeout period (t rp ) that can be selected via the factory fuse: 1.4 ms, 2 8 ms, 200 ms (default), or 1600 ms. figure 51 shows the behavior of the reset outputs, assuming that v out2 is selected as the rail to be monitored, and it supplies the external pullup connected to t he rsto output. t rp t rd v out2 v th v th v out2 1v 0v 0v v out2 rsto 11635-251 figure 51. reset timing diagram the ADP5051 has a dedicated sensing input pin (vth) to monitor the supply rail. the reset threshold at the vth input is typically 0.5 v. to monitor a voltage greater than 0. 5 v, connect a resistor divider network to the device. do not allow the vth input to float or be grounded. instead, connect the vth input to a supply voltage greater t han its specified threshold voltage. add a small capacitor on the vth input to improve the noise rejection and false rese t generation. when monitoring the input voltage, if the selected reset threshold falls below the internal vdd regulator uvlo level, the reset output ( rsto ) asserts low as soon as the internal vdd regulator falls below the uvlo threshold. the reset output is kept low down to ~1 v vdd to ensure that the reset output is not released when there is insufficient voltage on the rail, which th en supplies a processor to restart the processor operations. watchdog input the ADP5051 features a watchdog timer that monitors microprocessor activity. a timer circuit is cleared with every lowtohigh or hightolow logic transition on the watchdog input pin (wdi), which detects pulses as short as 80 ns. if the timer counts through the preset watchdog timeout pe riod (t wd ), reset is asserted. the microprocessor is required t o toggle the wdi pin to avoid being reset. therefore, failure of the microprocessor to toggle the wdi pin within the timeout period indica tes a code execution error, and the reset pulse generated rest arts the microprocessor in a known state. four options can b e selected for the watchdog timeout period (t wd ) via the factory fuse: 6.3 ms, 102 ms, 1600 ms (default), or 25.6 sec. in addition to a logic transition on the wdi pin, t he watchdog timer is also cleared by a reset assertion due to a n undervoltage condition on v out2 . when a reset is asserted, the watchdog timer is cleared, and the timer does not begin counting a gain until reset deasserts. the watchdog timer can be disabled by leaving the wdi pin floating or by threestating the wdi dr iver. figure 52 shows the watchdog timing diagram. v th v out2 v out2 wdi 1v 0v 0v 0v v out2 v out2 t rp t rp t wd rsto 11635-252 figure 52. watchdog timing diagram manual reset input the ADP5051 features a manual reset input ( mr pin, active low) with two operation modes available: processor manua l reset mode, or power on/off switch mode. the mr operation mode
ADP5051 preliminary technical data rev. prb | page 28 of 63 selection can be configured by factory fuse, and th e default setting is processor manual reset mode. the mr input has a 55 k, internal pullup resistor so tha t the input remains high when unconnected. to generate a reset, connect an external pushbutton switch between mr and ground. noise immunity is provided on the mr input, and fast, negativegoing transients of up to 100 ns (typical) are ignored. a 0.1 f capacitor between mr and ground provides additional noise immunity. processor manual reset mode in processor manual reset mode, when mr is driven low, the reset output is asserted. when mr transitions from low to high, the reset remains asserted for the duration of the rese t active timeout period (t rp ) before deasserting. figure 53 shows the mr behavior of the processor manual reset mode. mr mr externally driven low rsto v cc t rp t rp v rt v rt 11635-253 figure 53. mr timing diagram in processor reset mode power on/off switch mode in power on/off switch mode, when mr is driven low for more than 4 sec, all channels (when enabled) in the ADP5051 shut down, and pcrtl register are reset. in this shutdown standby condition, if mr is driven low for 500 ms again, all channels (when enabled) in the ADP5051 start up again according to the individual en pin status for a proper startup sequence on all channels. a writeonly code, 10101001, in register 0x10, force_shut can be used to overwrite the 4 sec mr timer to force all enabled channels to shut down earlier. in addition, this sh utdown code command can be used for a system shutdown command f rom the i 2 c host, even if the mr button is not pressed. when mr is driven low, the mr_st bit goes high to show the realtime manual reset status after the debounce ti mer. another mr_int bit is used for the interrupt output on the manual reset detected event for a possible coming shutdown. to c lear this mr_int status bit, write a1 into the status bit. in other words, this mr_int bit status is latched until above opera tion. figure 54 shows the mr timing diagram in power on/off switch mode. 500ms 4s t rp sequence start up sequence start up mr (used as on/off switch) mr_st (real-time mr status) mr_int (latched mr status for interrupt) vout1 to vout4 rsto mr shutdown by 4s mr timer mr shutdown status start up all powers by 500ms mr timer force rsto low in shutdown status vinx/enx t rp 1s blanking no mr_int interrupt in mr start up write 1 to clear 11635-254 figure 54. mr timing diagram in power on/off switch mode to prepare for an automatic startup next time, the mr shutdown condition can be cleared by any of the following co nditions: a power reset condition, all external enx pins pulled down, or an external enx pin pulled up. the manual reset on/off switch function allows the ADP5051 to send out an early shutdown warning signal to the ho st processor. after polling the realtime mr_st signal via the i 2 c interface, the host processor can decide and take the actions to prepare for the possible coming manual shutdown. usually the ho st processor can make an earlier forced shutdown to overwrite th e 4 sec timeout by the forced shutdown code; however, the 4 sec tim eout shutdown allows the system to properly shutdown in a process or brownout condition.
preliminary technical data ADP5051 rev. prb | page 29 of 63 i 2 c interface the ADP5051 includes an i 2 ccompatible serial interface for control of the power management blocks and for read back of system status (see figure 55). the i 2 c interface operates at clock frequencies of up to 400 khz. i 2 c register scl sda level shifter vddio vdd vddio uvlo_vddio trim data scp/ovp vddio vdd vdd vdd vddio 11635-051 figure 55. i 2 c interface block diagram note that the ADP5051 does not respond to general calls. the ADP5051 accepts multiple masters; however, if the device i s in read mode, access is limited to one master until the dat a transmission is completed. the i 2 c serial interface can be used to access the intern al registers of the ADP5051 . for complete information about the ADP5051 registers, see the register map section. sda and scl pins the ADP5051 has two dedicated i 2 c interface pins, sda and scl. sda is an opendrain line for receiving and tr ansmitting data. scl is an input line for receiving the clock signal. pull up these pins to the vddio supply using external resis tors. serial data is transferred on the rising edge of sc l. the read data is generated at the sda pin in read mode. i 2 c addresses the default 7bit i 2 c chip address for the ADP5051 is 0x4a (1001010 in binary). a different i 2 c address can be configured using the optional a0 pin that can replace the powe rgood functionality on pin 20. (for information about obtai ning an ADP5051 model with pin 20 functioning as the a0 pin, contac t your local analog devices sales or distribution rep resentative.) the a0 pin allows the use of two ADP5051 devices on the same i 2 c communication bus. figure 56 shows two ADP5051 devices configured with different i 2 c addresses using the a0 pin. scl vddio i 2 c interface i 2 c address = 0x4a i 2 c address = 0x4b a0 sda scl vddio a0 vreg sda 11635-050 figure 56. two ADP5051 devices configured with different i 2 c addresses (a0 function replaces pwrgd function on pin 20) selfclear register bits register 12 and register 14 are status registers that c ontain self clear register bits. these bits are cleared automat ically when 1 is written to the status bit. therefore, it is not nec essary to write 0 to the status bit to clear it.
ADP5051 preliminary technical data rev. prb | page 30 of 63 i 2 c interface timing diagrams figure 57 shows the timing diagram for the i 2 c write operation. figure 58 shows the timing diagram for the i 2 c read operation. the subaddress is used to select one of the user re gisters in the ADP5051 . the ADP5051 sends data to and from the register specified by the subaddress. scl chip address sda a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 a7 0 0 0 0 1 0 0 1 d0 d1 d2 d3 d4 d5 d6 d7 subaddress write data ack by slave write start ack by slave ack by slave r/w stop notes 1. maximum scl frequency is 400khz. 2. no response to general calls. output by processor output by ADP5051 11635-052 figure 57. i 2 c write to register scl chip address sda a0 a1 a2 a3 a4 a5 a6 a0 a1 a2 a3 a4 a5 a6 a7 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 d0 d1 d2 d3 d4 d5 d6 d7 subaddress chip address read data notes 1. maximum scl frequency is 400khz. 2. no response to general calls. output by processor output by ADP5051 ack by slave write start ack by slave read ack by slave no ack by master to stop reading r/w a0 a1 a2 a3 a4 a5 a6 r/w stop 11635-053 figure 58. i 2 c read from register
preliminary technical data ADP5051 rev. prb | page 31 of 63 applications information adisimpower design tool the ADP5051 is supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic and bi ll of materials and to calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and pa rt count while taking into consideration the operating conditions and limitations of the ic and all real external components. the adisimpower tool can be found at www.analog.com/adisimpower , and the user can request an unpopulated board through the t ool. programming the adjustable output voltage the output voltage of the ADP5051 is externally set by a resistive voltage divider from the output voltage to the fbx pin. to limit the degradation of the output voltage accuracy due to feedback bias current, ensure that the bottom resistor in th e divider is not too large; a value of less than 50 k is recommended . the equation for the output voltage setting is v out = v ref (1 + ( r top / r bot )) where: v out is the output voltage. v ref is the feedback reference voltage (0.8 v for channel 1 to channel 4). r top is the feedback resistor from v out to fbx. r bot is the feedback resistor from fbx to ground. no resistor divider is required in the fixed output options. each channel has vidx bits to program the output voltage for a specific range (see table 10). if a different fixed output vo ltage (default vid code) is required, contact your local analog de vices sales or distribution representative. voltage conversion limitations for a given input voltage, upper and lower limitati ons on the output voltage exist due to the minimum on time and the minimum off time. the minimum output voltage for a given input voltag e and switching frequency is limited by the minimum on ti me. the minimum on time for channel 1 and channel 2 is 117 ns (typical); the minimum on time for channel 3 and ch annel 4 is 90 ns (typical). the minimum on time increases at higher junction temperatures. note that in forced pwm mode, channel 1 and channel 2 can potentially exceed the nominal output voltage when the minimum on time limit is exceeded. careful switching freque ncy selection is required to avoid this problem. the minimum output voltage in continuous conduction mode (ccm) for a given input voltage and switching frequ ency can be calculated using the following equation: v out_min = v in t min_on f sw ? ( r dson1 ? r dson2 ) i out_min t min_on f sw ? ( r dson2 + r l ) i out_min (1) where: v out_min is the minimum output voltage. t min_on is the minimum on time. f sw is the switching frequency. r dson1 is the on resistance of the highside mosfet. r dson2 is the on resistance of the lowside mosfet. i out_min is the minimum output current. r l is the resistance of the output inductor. the maximum output voltage for a given input voltag e and switching frequency is limited by the minimum off t ime and the maximum duty cycle. note that the frequency fol dback feature helps to increase the effective maximum dut y cycle by lowering the switching frequency, thereby decreasin g the dropout voltage between the input and output voltages (see the frequency foldback section). the maximum output voltage for a given input voltag e and switching frequency can be calculated using the fol lowing equation: v out_max = v in (1 ? t min_off f sw ) ? ( r dson1 ? r dson2 ) i out_max (1 ? t min_off f sw ) ? ( r dson2 + r l ) i out_max (2) where: v out_max is the maximum output voltage. t min_off is the minimum off time. f sw is the switching frequency. r dson1 is the on resistance of the highside mosfet. r dson2 is the on resistance of the lowside mosfet. i out_max is the maximum output current. r l is the resistance of the output inductor. as shown in equation 1 and equation 2, reducing the switching frequency eases the minimum on time and off time li mitations. current limit setting the ADP5051 has three selectable current limit thresholds for channel 1 and channel 2. make sure that the selected current limit value is larger than the peak current of the inductor, i peak . see table 12 for the current limit configuration for channel 1 and channel 2.
ADP5051 preliminary technical data rev. prb | page 32 of 63 soft start setting the buck regulators in the ADP5051 include soft start circuitry that ramps the output voltage in a controlled manne r during startup, thereby limiting the inrush current. to se t the soft start time to a value of 2 ms, 4 ms, or 8 ms, connect a r esistor divider from the ss12 or ss34 pin to the vreg pin and ground (see the soft start section). inductor selection the inductor value is determined by the switching f requency, input voltage, output voltage, and inductor ripple current. using a small inductor value yields faster transient resp onse but degrades efficiency due to the larger inductor ripple curren t. using a large inductor value yields a smaller ripple current and better efficiency but results in slower transient response. thus, a t radeoff must be made between transient response and efficiency. as a guideline, the inductor ripple current, i l , is typically set to a value from 30% to 40% of the maximum load current. the inductor va lue can be calculated using the following equation: l = [( v in ? v out ) d ]/( i l f sw ) where: v in is the input voltage. v out is the output voltage. d is the duty cycle ( d = v out / v in ). i l is the inductor ripple current. f sw is the switching frequency. the ADP5051 has internal slope compensation in the current loop to prevent subharmonic oscillations when the d uty cycle is greater than 50%. because the internal current sen se signal is required, the inductor value recommended must not b e larger than 10 h for ch1 and ch2 or 22 h for ch3 and ch4. the peak inductor current is calculated using the f ollowing equation: i peak = i out + ( i l /2) the saturation current of the inductor must be larg er than the peak inductor current. for ferrite core inductors w ith a fast saturation characteristic, make sure that the satur ation current rating of the inductor is higher than the current l imit threshold of the buck regulator to prevent the inductor from becoming saturated. the rms current of the inductor can be calculated u sing the following equation: 12 2 2 l out rms i i i ? + = shielded ferrite core materials are recommended for low core loss and low emi. table 14 lists recommended inducto rs. table 14. recommended inductors vendor part no. value (h) i sat (a) i rms (a) dcr (m) size (mm) coilcraft xfl4020102 1.0 5.4 11 10.8 4 4 xfl4020222 2.2 3.7 8.0 21.35 4 4 xfl4020332 3.3 2.9 5.2 34.8 4 4 xfl4020472 4.7 2.7 5.0 52.2 4 4 xal4030682 6.8 3.6 3.9 67.4 4 4 xal4040103 10 3.0 3.1 84 4 4 xal6030102 1.0 23 18 5.62 6 6 xal6030222 2.2 15.9 10 12.7 6 6 xal6030332 3.3 12.2 8.0 19.92 6 6 xal6060472 4.7 10.5 11 14.4 6 6 xal6060682 6.8 9.2 9.0 18.9 6 6 toko fdv05301r0 1.0 11.2 9.1 9.4 6.2 5.8 fdv05302r2 2.2 7.1 7.0 17.3 6.2 5.8 fdv05303r3 3.3 5.5 5.3 29.6 6.2 5.8 fdv05304r7 4.7 4.6 4.2 46.6 6.2 5.8 output capacitor selection the selected output capacitor affects both the outp ut voltage ripple and the loop dynamics of the regulator. for example, during load step transients on the output, when the load is suddenly increased, the output capacitor supplies t he load until the control loop can ramp up the inductor current, causing an undershoot of the output voltage. the output capacitance required to meet the undersh oot (voltage droop) requirement can be calculated using the following equation: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = where: k uv is a factor (typically set to 2). i step is the load step. v out_uv is the allowable undershoot on the output voltage. another example of the effect of the output capacit or on the loop dynamics of the regulator is when the load is suddenly removed from the output and the energy stored in th e inductor rushes into the output capacitor, causing an oversh oot of the output voltage. the output capacitance required to meet the oversho ot requirement can be calculated using the following e quation:
preliminary technical data ADP5051 rev. prb | page 33 of 63 ( ) 2 2 2 _ out out_ov out step ov ov out v v v l i k c ? ? + ? = where: k ov is a factor (typically set to 2). i step is the load step. v out_ov is the allowable overshoot on the output voltage. the equivalent series resistance (esr) of the outpu t capacitor and its capacitance value determine the output volt age ripple. use the following equations to select a capacitor t hat can meet the output ripple requirements: ripple out sw l ripple out v f i c _ _ 8 ? ? = l ripple out esr i v r ? ? = _ where: i l is the inductor ripple current. f sw is the switching frequency. v out_ripple is the allowable output voltage ripple. r esr is the equivalent series resistance of the output capacitor. select the largest output capacitance given by c out_uv , c out_ov , and c out_ripple to meet both load transient and output ripple requirements. the voltage rating of the selected output capacitor must be greater than the output voltage. the minimum rms cu rrent rating of the output capacitor is determined by the following equation: 12 _ l rms c i i out ? = input capacitor selection the input decoupling capacitor attenuates high freq uency noise on the input and acts as an energy reservoir. use a ce ramic capacitor and place it close to the pvinx pin. keep the loop composed of the input capacitor, the highside nfet, and the lo wside nfet as small as possible. the voltage rating of the inp ut capacitor must be greater than the maximum input voltage. mak e sure that the rms current rating of the input capacitor is la rger than the following equation: ( ) d d i i out rms c in ? = 1 _ where d is the duty cycle ( d = v out / v in ). lowside power device selection channel 1 and channel 2 include integrated lowside mosfet drivers that can drive lowside nchannel mosfets ( nfets). the selection of the lowside nchannel mosfet affe cts the performance of the buck regulator. the selected mosfet must meet the following require ments: ? draintosource voltage (v ds ) must be higher than 1.2 v in . ? drain current (i d ) must be greater than 1.2 i limit_max , where i limit_max is the selected maximum current limit threshold. ? the selected mosfet can be fully turned on at v gs = 4.5 v. ? total gate charge (qg at v gs = 4.5 v) must be less than 20 nc. lower qg characteristics provide higher efficiency. when the highside mosfet is turned off, the lowsi de mosfet supplies the inductor current. for low duty cycle a pplications, the lowside mosfet supplies the current for most of th e period. to achieve higher efficiency, it is important to se lect a mosfet with low on resistance. the power conduction loss f or the low side mosfet can be calculated using the following e quation: p fet_low = i out 2 r dson (1 ? d ) where: r dson is the on resistance of the lowside mosfet. d is the duty cycle ( d = v out / v in ). table 15 lists recommended dual mosfets for various current limit settings. ensure that the mosfet can handle t hermal dissipation due to power loss. table 15. recommended dual mosfets vendor part no. v ds (v) i d (a) r dson (m) qg (nc) size (mm) ir irfhm8363 30 10 20.4 6.7 3 3 irlhs6276 20 3.4 45 3.1 2 2 fairchild fdma1024 20 5.0 54 5.2 2 2 fdmb3900 25 7.0 33 11 3 2 fdmb3800 30 4.8 51 4 3 2 fdc6401 20 3.0 70 3.3 3 3 vishay si7228dn 30 23 25 4.1 3 3 si7232dn 20 25 16.4 12 3 3 si7904bdn 20 6 30 9 3 3 si5906du 30 6 40 8 3 2 si5908dc 20 5.9 40 5 3 2 sia906edj 20 4.5 46 3.5 2 2 aos aon7804 30 22 26 7.5 3 3 aon7826 20 22 26 6 3 3 ao6800 30 3.4 70 4.7 3 3 aon2800 20 4.5 47 4.1 2 2 programming the uvlo input the precision enable input can be used to program t he uvlo threshold of the input voltage, as shown in figure 38. to limit the degradation of the input voltage accuracy due t o the internal 1 m pulldown resistor tolerance, ensure that the bottom
ADP5051 preliminary technical data rev. prb | page 34 of 63 resistor in the divider is not too large; a value o f less than 50 k is recommended. the precision turnon threshold is 0.8 v. the resis tive voltage divider for the programmable v in startup voltage is calculated as follows: ) m 1 + m 1 + ( )) v/ (0.8 + na (0.8 = bot_en bot_en top_en bot_en in_startup r r r r v where: r top_en is the resistor from v in to en. r bot_en is the resistor from en to ground. compensation components design for the peak current mode control architecture, the power stage can be simplified as a voltage controlled cur rent source that supplies current to the output capacitor and l oad resistor. the simplified loop is composed of one domain pole and a zero contributed by the output capacitor esr. the contro ltooutput transfer function is shown in the following equatio ns: ? ?? ? ? ?? ? + ? ?? ? ? ?? ? + = = p z vi comp out vd f s f s r a s v s v s g 2 1 2 1 ) ( ) ( ) ( out esr z c r f = 2 1 ( ) out esr p c r r f + = 2 1 where: a vi = 10 a/v for channel 1 or channel 2, and 3.33 a/v for channel 3 or channel 4. r is the load resistance. r esr is the equivalent series resistance of the output capacitor. c out is the output capacitance. the ADP5051 uses a transconductance amplifier as the error amplifier to compensate the system. figure 59 shows the simplified peak current mode control small signal circuit. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 11635-054 figure 59. simplified peak current mode control sma ll signal circuit the compensation components, r c and c c , contribute a zero; r c and the optional c cp contribute an optional pole. the closedloop transfer equation is as follows: ) ( 1 1 ) ( s g s c c c c r s s c r c c g r r r s t vd cp c cp c c c c cp c m top bot bot v ? ?? ? ? ?? ? + + + + ? + = the following guidelines show how to select the com pensation components (r c , c c , and c cp ) for ceramic output capacitor applications. 1. determine the cross frequency (f c ). generally, f c is between f sw /12 and f sw /6. 2. calculate r c using the following equation: vi m c out out c a g f c v r = v 8.0 2 3. place the compensation zero at the domain pole (f p ). calculate c c using the following equation: ( ) c out esr c r c r r c + = 4. c cp is optional. it can be used to cancel the zero cau sed by the esr of the output capacitor. calculate c cp using the following equation: c out esr cp r c r c = power dissipation the total power dissipation in the ADP5051 simplifies to p d = p buck1 + p buck2 + p buck3 + p buck4 buck regulator power dissipation the power dissipation (p loss ) for each buck regulator includes power switch conduction losses (p cond ), switching losses (p sw ),
preliminary technical data ADP5051 rev. prb | page 35 of 63 and transition losses (p tran ). other sources of power dissipation exist, but these sources are generally less signifi cant at the high output currents of the application thermal limit. use the following equation to estimate the power di ssipation of the buck regulator: p loss = p cond + p sw + p tran power switch conduction loss (p cond ) power switch conduction losses are caused by the fl ow of output current through both the highside and lowside pow er switches, each of which has its own internal on resistance (r dson ). use the following equation to estimate the power sw itch conduction loss: p cond = ( r dson_hs d + r dson_ls (1 ? d )) i out 2 where: r dson_hs is the on resistance of the highside mosfet. r dson_ls is the on resistance of the lowside mosfet. d is the duty cycle ( d = v out / v in ). switching loss (p sw ) switching losses are associated with the current dr awn by the driver to turn the power devices on and off at the switching frequency. each time a power device gate is turned on or off, the driver transfers a charge from the input supply to the gate, and then from the gate to ground. use the following equation to estimate the switching loss: p sw = ( c gate_hs + c gate_ls ) v in 2 f sw where: c gate_hs is the gate capacitance of the highside mosfet. c gate_ls is the gate capacitance of the lowside mosfet. f sw is the switching frequency. transition loss (p tran ) transition losses occur because the highside mosfe t cannot turn on or off instantaneously. during a switch nod e transition, the mosfet provides all the inductor current. the s ourceto drain voltage of the mosfet is half the input volta ge, resulting in power loss. transition losses increase with both load and input voltage and occur twice for each switching cycle. u se the following equation to estimate the transition loss: p tran = 0.5 v in i out ( t r + t f ) f sw where: t r is the rise time of the switch node. t f is the fall time of the switch node. thermal shutdown channel 1 and channel 2 store the value of the indu ctor current only during the on time of the internal highside m osfet. therefore, a small amount of power (as well as a sm all amount of input rms current) is dissipated inside the ADP5051 , which reduces thermal constraints. however, when channel 1 and channel 2 are operating under maximum load with high ambient temperature and high duty cycle, the input rms current can become very large and cause the junction temperature to exceed the maximum junc tion temperature of 125c. if the junction temperature e xceeds 150c, the regulator enters thermal shutdown and re covers when the junction temperature falls below 135c.
ADP5051 preliminary technical data rev. prb | page 36 of 63 junction temperature the junction temperature of the die is the sum of t he ambient temperature of the environment and the temperature rise of the package due to power dissipation, as shown in the f ollowing equation: t j = t a + t r where: t j is the junction temperature. t a is the ambient temperature. t r is the rise in temperature of the package due to p ower dissipation. the rise in temperature of the package is directly proportional to the power dissipation in the package. the propor tionality constant for this relationship is the thermal resis tance from the junction of the die to the ambient temperature, as shown in the following equation: t r = ja p d where: t r is the rise in temperature of the package. ja is the thermal resistance from the junction of the die to the ambient temperature of the package (see table 7). p d is the power dissipation in the package. an important factor to consider is that the thermal resistance value is based on a 4layer, 4 inch 3 inch pcb wi th 2.5 oz. of copper, as specified in the jedec standard, whereas realworld applications may use pcbs with different dimensions and a different number of layers. it is important to maximize the amount of copper us ed to remove heat from the device. copper exposed to air dissipa tes heat better than copper used in the inner layers. connect the e xposed pad to the ground plane with several vias.
preliminary technical data ADP5051 rev. prb | page 37 of 63 design example this section provides an example of the stepbyste p design procedures and the external components required for channel 1. table 16 lists the design requirements for this exa mple. table 16. example design requirements for channel 1 parameter specification input voltage v pvin1 = 12 v 5% output voltage v out1 = 1.2 v output current i out1 = 4 a output ripple v out1_ripple = 12 mv in ccm mode load transient 5% at 20% to 80% load transient, 1 a/s although this example shows stepbystep design pro cedures for channel 1, the procedures apply to all other bu ck regulator channels (channel 2 to channel 4). setting the switching frequency the first step is to determine the switching freque ncy for the ADP5051 design. in general, higher switching frequencies produce a smaller solution size due to the lower co mponent values required, whereas lower switching frequencie s result in higher conversion efficiency due to lower switching losses. the switching frequency of the ADP5051 can be set to a value from 250 khz to 1.4 mhz by connecting a resistor fr om the rt pin to ground. the selected resistor allows the use r to make decisions based on the tradeoff between efficiency and solution size. (for more information, see the oscillator sec tion.) however, the highest supported switching frequency must be a ssessed by checking the voltage conversion limitations enforce d by the minimum on time and the minimum off time (see the v oltage conversion limitations section). in this design example, a switching frequency of 60 0 khz is used to achieve a good combination of small solutio n size and high conversion efficiency. to set the switching fr equency to 600 khz, use the following equation to calculate th e resistor value, r rt : r rt (k) = [14,822/ f sw (khz)] 1.081 therefore, select standard resistor r rt = 31.6 k. setting the output voltage select a 10 k bottom resistor (r bot ) and then calculate the top feedback resistor using the following equation: r bot = r top ( v ref /( v out ? v ref )) where: v ref is 0.8 v for channel 1. v out is the output voltage. to set the output voltage to 1.2 v, choose the foll owing resistor values: r top = 4.99 k and r bot = 10 k. setting the current limit for 4 a output current operation, the typical peak current limit is 6.44 a. for this example, choose r ilim1 = 22 k (see table 12). for more information, see the current limit protect ion section. selecting the inductor the peaktopeak inductor ripple current, i l , is set to 35% of the maximum output current. use the following equat ion to estimate the value of the inductor: l = [( v in ? v out ) d ]/( i l f sw ) where: v in = 12 v. v out = 1.2 v. d is the duty cycle ( d = v out / v in = 0.1). i l = 35% 4 a = 1.4 a. f sw = 600 khz. the resulting value for l is 1.28 h. the closest s tandard inductor value is 1.5 h; therefore, the inductor r ipple current, i l , is 1.2 a. the peak inductor current is calculated using the f ollowing equation: i peak = i out + ( i l /2) the calculated peak current for the inductor is 4.6 a. the rms current of the inductor can be calculated u sing the following equation: 12 2 2 l out rms i i i ? + = the rms current of the inductor is approximately 4. 02 a. therefore, an inductor with a minimum rms current r ating of 4.02 a and a minimum saturation current rating o f 4.6 a is required. however, to prevent the inductor from rea ching its saturation point in current limit conditions, it is recommended that the inductor saturation current be higher than the maximum peak current limit, typically 7.48 a, for reliable operation. based on these requirements and recommendations, th e toko fdv05301r5, with a dcr of 13.5 m, is selecte d for this design. selecting the output capacitor the output capacitor must meet the output voltage r ipple and load transient requirements. to meet the output vol tage ripple requirement, use the following equations to calcula te the esr and capacitance: ripple out sw l ripple out v f i c _ _ 8 ? ? =
ADP5051 preliminary technical data rev. prb | page 38 of 63 l ripple out esr i v r ? ? = _ the calculated capacitance, c out_ripple , is 20.8 f, and the calculated r esr is 10 m. to meet the 5% overshoot and undershoot requiremen ts, use the following equations to calculate the capaci tance: ( ) uv out out in step uv uv out v v v l i k c _ 2 _ 2 ? ? ? = ( ) 2 2 2 _ out out_ov out step ov ov out v v v l i k c ? ? + ? = for estimation purposes, use k ov = k uv = 2; therefore, c out_ov = 117 f and c out_uv = 13.3 f. the esr of the output capacitor must be less than 1 3.3 m, and the output capacitance must be greater than 117 f. it is recommended that three ceramic capacitors be used ( 47 f, x5r, 6.3 v), such as the grm21br60j476me15 from mur ata with an esr of 2 m. selecting the lowside mosfet a low r dson nchannel mosfet must be selected for high efficiency solutions. the mosfet breakdown voltage (v ds ) must be greater than 1.2 v in , and the drain current must be greater than 1.2 i limit_max . it is recommended that a 20 v, dual nchannel mosfe t, such as the si7232dn from vishay, be used for both chann el 1 and channel 2. the r dson of the si7232dn at 4.5 v driver voltage is 16.4 m, and the total gate charge is 12 nc. designing the compensation network for better load transient and stability performance , set the cross frequency, f c , to f sw /10. in this example, f sw is set to 600 khz; therefore, f c is set to 60 khz. for the 1.2 v output rail, the 47 f ceramic output capacitor has a derated value of 40 f. k 4. 14 a/v 10 s 470 v 8.0 khz 60 f 40 3 v 2 . 1 2 = = c r ( ) nf 51 .2 k 4. 14 f 40 3 001 . 0 3 . 0 = + = c c pf 3.8 k 4. 14 f 40 3 001 . 0 = = cp c choose standard components: r c = 15 k and c c = 2.7 nf. c cp is optional. figure 60 shows the bode plot for the 1.2 v output rail. the cross frequency is 62 khz, and the phase margin is 58. figure 61 shows the load transient waveform. 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 120 ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 62khz phase margin: 58 11635-161 figure 60. bode plot for 1.2 v output ch1 50.0mv b w ch4 2.00a b w m200s a ch4 2.32a 1 4 v out i out 11635-162 figure 61. 0.8 a to 3.2 a load transient for 1.2 v output selecting the soft start time the soft start feature allows the output voltage to ramp up in a controlled manner, eliminating output voltage overs hoot during soft start and limiting the inrush current. the ss12 pin can be used to program a soft start ti me of 2 ms, 4 ms, or 8 ms and can be used to configure parallel operation of channel 1 and channel 2. for more information, see the soft start section and table 11. selecting the input capacitor for the input capacitor, select a ceramic capacitor with a minimum value of 10 f; place the input capacitor close to the pvin1 pin. in this example, one 10 f, x5r, 25 v ceramic capac itor is recommended. recommended external components table 17 lists the recommended external components for 4 a applications used with channel 1 and channel 2 of t he ADP5051 . table 18 lists the recommended external components for 1.2 a applications used with channel 3 and channel 4.
preliminary technical data ADP5051 rev. prb | page 39 of 63 table 17. recommended external components for typic al 4 a applications, channel 1 and channel 2 (1% o utput ripple, 7.5% tolerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k) r bot (k) r c (k) c c (pf) dual fet 300 4 12 (or 5) 1.2 3.3 2 100 1 4.99 10 10 4700 si7232dn 12 (or 5) 1.5 3.3 2 100 1 8.87 10.2 10 4700 si7232dn 12 (or 5) 1.8 3.3 3 47 2 12.7 10.2 6.81 4700 si7232dn 12 (or 5) 2.5 4.7 3 47 2 21.5 10.2 10 4700 si7232dn 12 (or 5) 3.3 6.8 3 47 2 31.6 10.2 10 4700 si7232dn 12 5.0 6.8 47 3 52.3 10 4.7 4700 si7232dn 600 4 12 (or 5) 1.2 1.5 2 47 2 4.99 10 10 2700 si7232dn 12 (or 5) 1.5 1.5 2 47 2 8.87 10.2 10 2700 si7232dn 12 (or 5) 1.8 2.2 2 47 2 12.7 10.2 10 2700 si7232dn 12 (or 5) 2.5 2.2 2 47 2 21.5 10.2 10 2700 si7232dn 12 (or 5) 3.3 3.3 2 47 2 31.6 10.2 15 2700 si7232dn 12 5.0 3.3 47 3 52.3 10 10 2700 si7232dn 1000 4 5 1.2 1.0 2 47 2 4.99 10 15 1500 si7232dn 5 1.5 1.0 2 47 2 8.87 10.2 15 1500 si7232dn 12 (or 5) 1.8 1.0 47 2 12.7 10.2 10 1500 si7232dn 12 (or 5) 2.5 1.5 47 2 21.5 10.2 10 1500 si7232dn 12 (or 5) 3.3 1.5 47 2 31.6 10.2 10 1500 si7232dn 12 5.0 2.2 47 3 52.3 10 15 1500 si7232dn 1 100 f capacitor: murata grm31cr60j107me39 (6.3 v, x5r, 1206). 2 47 f capacitor: murata grm21br60j476me15 (6.3 v, x 5r, 0805). 3 47 f capacitor: murata grm31cr61a476me15 (10 v, x5 r, 1206). table 18. recommended external components for typic al 1.2 a applications, channel 3 and channel 4 (1% output ripple, 7.5% tolerance at ~60% step transient) f sw (khz) i out (a) v in (v) v out (v) l (h) c out (f) r top (k) r bot (k) r c (k) c c (pf) 300 1.2 12 (or 5) 1.2 10 2 22 1 4.99 10 6.81 4700 12 (or 5) 1.5 10 2 22 1 8.87 10.2 6.81 4700 12 (or 5) 1.8 15 2 22 1 12.7 10.2 6.81 4700 12 (or 5) 2.5 15 2 22 1 21.5 10.2 6.81 4700 12 (or 5) 3.3 22 2 22 1 31.6 10.2 6.81 4700 12 5.0 22 22 2 52.3 10 6.81 4700 600 1.2 12 (or 5) 1.2 4.7 22 1 4.99 10 6.81 2700 12 (or 5) 1.5 6.8 22 1 8.87 10.2 6.81 2700 12 (or 5) 1.8 6.8 22 1 12.7 10.2 6.81 2700 12 (or 5) 2.5 10 22 1 21.5 10.2 6.81 2700 12 (or 5) 3.3 10 22 1 31.6 10.2 6.81 2700 12 5.0 10 22 2 52.3 10 6.81 2700 1000 1.2 5 1.2 2.2 22 1 4.99 10 10 1800 12 (or 5) 1.5 3.3 22 1 8.87 10.2 10 1800 12 (or 5) 1.8 4.7 22 1 12.7 10.2 10 1800 12 (or 5) 2.5 4.7 22 1 21.5 10.2 10 1800 12 (or 5) 3.3 6.8 22 1 31.6 10.2 10 1800 12 5.0 6.8 22 2 52.3 10 15 1800 1 22 f capacitor: murata grm188r60j226mea0 (6.3 v, x 5r, 0603). 2 22 f capacitor: murata grm219r61a226mea0 (10 v, x5 r, 0805).
ADP5051 preliminary technical data rev. prb | page 40 of 63
preliminary technical data ADP5051 rev. prb | page 41 of 63 circuit board layout recommendations good circuit board layout is essential to obtain th e best perfor mance from the ADP5051 (see figure 63). poor layout can affect the regulation and stability of the part, as well a s the electro magnetic interference (emi) and electromagnetic com patibility (emc) performance. refer to the following guideline s for a good pcb layout. ? place the input capacitor, inductor, mosfet, output capacitor, and bootstrap capacitor close to the ic. ? use short, thick traces to connect the input capaci tors to the pvinx pins and use dedicated power ground to co nnect the input and output capacitor grounds to minimize the connection length. ? use several high current vias, if required, to conn ect pvinx, pgndx, and swx to other power planes. ? use short, thick traces to connect the inductors to the swx pins and the output capacitors. ? ensure that the high current loop traces are as sho rt and wide as possible. figure 62 shows the high current path. ? maximize the amount of ground metal for the exposed pad and use as many vias as possible on the component s ide to improve thermal dissipation. ? use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. ? place the decoupling capacitors close to the vreg a nd vdd pins. ? place the frequency setting resistor close to the r t pin. ? place the feedback resistor divider close to the fb x pin. in addition, keep the fbx traces away from the high cu rrent traces and the switch node to avoid noise pickup. ? use 0402 or 0603 size resistors and capacitors to a chieve the smallest possible footprint solution on boards where space is limited. v in v out pvinx enx pgnd bstx swx ADP5051 dlx fbx 11635-055 figure 62. typical circuit with high current traces shown in blue ADP5051 12 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 l1 l3 l4 c 04 0 2 r 0 40 2 0.1 f 6 .3v /x r 5 04 0 2 sw2 sw2 b s t 2 pvin2 pvin2 dl2 pgnd dl1 pvin1 bst1 sw1 sw1 pvin1 r 04 0 2 g1 s2 g2 d1 d2 d2 d1 s1 dual mosfet r 0 4 02 en2 fb2 comp2 comp4 fb4 en4 bst4 pgnd4 sw4 pvin4 vth rsto mr wdi pvin3 sw3 pgnd3 bst3 vreg en1 fb1 comp1 ss12 rt sync/ mode fb3 en3 pwrgd gnd comp3 r 04 0 2 c 04 0 2 r 04 0 2 c 0 40 2 r 0 4 02 r 0 40 2 0 .1 f 6 .3 v/x r 5 0 40 2 0 .1 f 6 .3 v/x r 5 0 40 2 0 .1f 6 .3 v /xr 5 0 4 02 ss34 r 04 0 2 1 f 6 .3 v /xr 5 0 4 02 c 0 40 2 r 04 0 2 vdd 1 f 6 .3 v /xr 5 0 4 02 r 04 0 2 r 0 40 2 r 0 4 02 r 0 4 02 r 0 4 02 r 0 40 2 r 0 40 2 r 0 4 02 l2 vout4 vout3 vout2 vout1 scl sda vddio c 0 4 02 r 04 0 2 11635-263 cinx: 10f, 25v/xr5, 0805 coutx: 22f, 6.3v/xr5, 0805 cinx: 10f, 25v/xr5, 0805 cinx: 10f, 25v/xr5, 0805 cinx: 10f, 25v/xr5, 0805 coutx: 47f, 6.3v/xr5, 0805 coutx: 47f, 6.3v/xr5, 0805 coutx: 22f, 6.3v/xr5, 0805 figure 63. typical pcb layout for the ADP5051
ADP5051 preliminary technical data rev. prb | page 42 of 63 typical application circuits 11635-264 1.1v~1.3v/2.5a (dvs) 3.3v/2.5a 4.0v~4.5v/1.2a (dvs) processor ddr memory rfpa rf transceiver vcore i/o ddr term. ldo ch2 buck (1.2a/2.5a/4a) ch1 buck (1.2a/2.5a/4a) i 2 c ch4 buck (1.2a) osc int vreg 100ma q1 5vreg q2 l1 l2 5vreg rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 alert l4 bst4 sw4 fb4 pgnd4 int pvin1 comp1 en1 pvin2 comp2 en2 pvin3 ss34 comp3 en3 pvin4 comp4 en4 sda exposed pad c2 10f c3 0.1f c5 10f c8 10f c11 10f 12v vout1 vout2 vout3 vout4 2.2h vddio 31.6k vddio int scl sda sia906edj (46m ) scl pwrgd vreg vdd ss12 vout1 vreg vreg sync/mode vreg 4.7nf 4.7k 4.7nf 4.7k 2.7nf 6.81k 2.7nf 6.81k vth rsto mr 10k 10k wdi vreg sda scl int 10k watchdog and reset c0 1.0f c1 1.0f ch3 buck (1.2a) c4 47f c7 47f c10 22f c13 22f c6 0.1f c9 0.1f c12 0.1f 4.7h 6.8h 10h 1.5v/1.2a ADP5051 figure 64. typical femtocell application, 600 khz s witching frequency, fixed output model
preliminary technical data ADP5051 rev. prb | page 43 of 63 11635-265 q1 5vreg q2 l1 l2 5vreg sync/mode rt fb1 bst1 sw1 dl1 dl2 pgnd sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 alert l4 bst4 sw4 fb4 pgnd4 int comp1 pvin2 comp2 en2 pvin3 comp3 en3 pvin4 comp4 en4 sda exposed pad c2 10f c3 0.1f c5 10f c8 10f c11 10f c6 0.1f c9 0.1f c7 47f c12 0.1f c13 22f c10 22f vout1 vout2 vout3 vout4 22k 22k 1.5h 6.8h 10h vddio 31.6k scl pwrgd 1.5v/1.2a 2.5v/4a 1.2v/4a 3.3v/1.2a fpga flash memory vcore auxiliary voltage ddr term. ldo ddr3 memory c18 47f c4 47f vreg vdd ss ss34 vreg vreg vreg 4.7nf 10k 10k 4.7nf 2.7nf c19 47f 10k 4.99k 10.2k 21.5k 10.2k 8.87k 6.81k 2.7nf 6.81k vth rsto mr 10k 11k wdi vreg 10k vout1 gpio reset rsto wdi si7232dn (16.4m ) i/os i/os bank 0 bank 1 bank 2 bank 3 i 2 c watchdog and reset osc int vreg 100ma pvin1 12v c0 1.0f c1 1.0f ch2 buck (1.2a/2.5a/4a) ch1 buck (1.2a/2.5a/4a) ch4 buck (1.2a) ch3 buck (1.2a) en1 2.2h 31.6k 10.2k ADP5051 figure 65. typical fpga application, 600 khz switch ing frequency, adjustable output model
ADP5051 preliminary technical data rev. prb | page 44 of 63 11635-266 watchdog and reset i 2 c osc q1 5vreg 5vreg q2 l1 l2 sync/mode rt fb1 bst1 sw1 dl1 pgnd dl2 sw2 bst2 fb2 l3 bst3 sw3 fb3 pgnd3 alert l4 bst4 sw4 fb4 pgnd4 vth rsto int pvin1 comp1 en1 pvin2 comp2 en2 pvin3 comp3 en3 pvin4 comp4 en4 sda exposed pad c2 10f c5 10f c8 10f c11 10f c4 100f c3 0.1f c6 0.1f c9 0.1f c10 22f c13 22f c12 0.1f 12v vout1 vout3 vout4 22k 22k 1.5h 6.8h 10h vddio 31.6k scl pwrgd mr 1.2v/8a 1.5v/1.2a c18 100f vreg c1 1.0f c0 1.0f vdd int vreg 100ma ss12 ss34 vreg vreg vreg 4.7nf 10k 10k 4.99k 10.2k 8.87k 10.2k 31.6k 51k 10k 2.7nf 6.81k 2.7nf 6.81k 100k 600k wdi vreg 10k si7232dn (16.4m ) ch2 buck (1.2a/2.5a/4a) ch1 buck (1.2a/2.5a/4a) ch4 buck (1.2a) ch3 buck (1.2a) 3.3v/1.2a 1.5h ADP5051 figure 66. typical channel 1/channel 2 parallel out put application, 600 khz switching frequency, adjus table output model
preliminary technical data ADP5051 rev. prb | page 45 of 63 register map table 19. register map register number register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0x00 reserved reserved 1 0x01 pctrl reserved ch4_on ch3_on ch2_on ch1_on 2 0x02 vid1 reserved vid1[4:0] 3 0x03 vid23 reserved vid3[2:0] reserved vid2[2:0] 4 0x04 vid4 reserved vid4[4:0] 5 0x05 dvs_cfg reserved dvs4_on dvs4_intval[1:0] re served dvs1_on dvs1_intval[1:0] 6 0x06 opt_cfg dscg4_on dscg3_on dscg2_on dscg1_on psm4_on psm3_on psm2_on psm1_on 7 0x07 lch_cfg ovp4_on ovp3_on ovp2_on ovp1_on scp4 _on scp3_on scp2_on scp1_on 8 0x08 sw_cfg freq3 freq1 phase4[1:0] phase3[1:0] p hase2[1:0] 9 0x09 th_cfg reserved temp_th[1:0] lvin_th[3:0] 10 0x0a hiccup_cfg sync_out reserved hiccup4_off hi ccup3_off hiccup2_off hiccup1_off 11 0x0b pwrgd_mask reserved mask_ch4 mask_ch3 mask_ch2 mask_ch1 12 0x0c lch_status reserved tsd_lch ch4_lch ch3_lch ch2_lch ch1_lch 13 0x0d status_rd reserved mr_st reserved pwrg4 pwr g3 pwrg2 pwrg1 14 0x0e int_status reserved mr_int temp_int lvin_in t pwrg4_int pwrg3_int pwrg2_int pwrg1_int 15 0x0f int_mask reserved mask_mr mask_temp mask_lvin mask_pwrg4 mask_pwrg3 mask_pwrg2 mask_pwrg1 16 0x10 force_shut force_shut[7:0] 17 0x11 default_set default_set[7:0]
ADP5051 preliminary technical data rev. prb | page 46 of 63 detailed register descriptions this section describes the bit functions of each re gister used by the ADP5051 . to reset a register, the internal vdd poweron reset signals must be low, unless otherwise noted. register 1: pctrl (channel enable control), address 0x01 register 1 is used to enable and disable the operat ion of each channel. the on or off status of a channel is contr olled by the chx_on bit in this register and the external hardwa re enable pin for the channel (logical and). the default valu e of the chx_on bit, 1, means that the channel enable is con trolled by the external hardware enable pin. the channel can b e disabled or enabled via the i 2 c interface only when the enx pin is high. pulling the enx pin low resets the corresponding ch x_on bit to the default value (1) to allow another valid sta rtup when the enx pin is high again. table 20. register 1 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ch4_on ch3_on ch2_on ch1_on table 21. pctrl register bit function descriptions bits bit name access description [7:4] reserved r/w reserved. 3 ch4_on r/w 0 = disable channel 4 (en4 pin must be high). 1 = enable channel 4 (default). 2 ch3_on r/w 0 = disable channel 3 (en3 pin must be high). 1 = enable channel 3 (default). 1 ch2_on r/w 0 = disable channel 2 (en2 pin must be high). 1 = enable channel 2 (default). 0 ch1_on r/w 0 = disable channel 1 (en1 pin must be high). 1 = enable channel 1 (default). register 2: vid1 (vid setting for channel 1), addre ss 0x02 register 2 is used to set the output voltage for ch annel 1. table 22. register 2 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved vid1[4:0] table 23. vid1 register bit function descriptions bits bit name access description [7:5] reserved r/w reserved. [4:0] vid1[4:0] r/w these bits set the output volta ge for channel 1. the default value is programmed b y factory fuse. 00000 = 0.8 v (adjustable). 00001 = 0.85 v. 00010 = 0.875 v. 00011 = 0.9 v. 00111 = 1.0 v. 10011 = 1.3 v. 11011 = 1.5 v. 11110 = 1.575 v. 11111 = 1.6 v.
preliminary technical data ADP5051 rev. prb | page 47 of 63 register 3: vid23 (vid setting for channel 2 and ch annel 3), address 0x03 register 3 is used to set the output voltage for ch annel 2 and channel 3. table 24. register 3 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved vid3[2:0] reserved vid2[2:0] table 25. vid23 register bit function descriptions bits bit name access description 7 reserved r/w reserved. [6:4] vid3[2:0] r/w these bits set the output volta ge for channel 3. the default value is programmed b y factory fuse. 000 = 0.8 v (adjustable). 001 = 1.2 v. 010 = 1.3 v. 011 = 1.4 v. 100 = 1.5 v. 101 = 1.6 v. 110 = 1.7 v. 111 = 1.8 v. 3 reserved r/w reserved. [2:0] vid2[2:0] r/w these bits set the output volta ge for channel 2. the default value is programmed b y factory fuse. 000 = 0.8 v (adjustable). 001 = 3.3 v. 010 = 3.6 v. 011 = 3.9 v. 100 = 4.2 v. 101 = 4.5 v. 110 = 4.8 v. 111 = 5.0 v. register 4: vid4 (vid setting for channel 4), addre ss 0x04 register 4 is used to set the output voltage for ch annel 4. table 26. register 4 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved vid4[4:0] table 27. vid4 register bit function descriptions bits bit name access description [7:5] reserved r/w reserved. [4:0] vid4[4:0] r/w these bits set the output volta ge for channel 4. the default value is programmed b y factory fuse. 00000 = 0.8 v (adjustable). 00001 = 2.5 v. 00010 = 2.6 v. 00110 = 3.0 v. 10000 = 4.0 v.
ADP5051 preliminary technical data rev. prb | page 48 of 63 bits bit name access description 11010 = 5.0 v. 11110 = 5.4 v. 11111 = 5.5 v. register 5: dvs_cfg (dvs configuration for channel 1 and channel 4), address 0x05 register 5 is used to configure the dynamic voltage scaling (dvs) for channel 1 and channel 4 (see the dynamic voltage scaling (dvs) section). table 28. register 5 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dvs4_on dvs4_intval[1:0] reserved dvs1_on dvs1_intval[1:0] table 29. dvs_cfg register bit function description s bits bit name access description 7 reserved r/w reserved 6 dvs4_on r/w 0 = disable dvs for channel 4 (defaul t) 1 = enable dvs for channel 4 [5:4] dvs4_intval[1:0] r/w configures the dvs inter val for channel 4 00 = 62.5 s (default) 01 = 31.2 s 10 = 15.6 s 11 = 7.8 s 3 reserved r/w reserved 2 dvs1_on r/w 0 = disable dvs for channel 1 (defaul t) 1 = enable dvs for channel 1 [1:0] dvs1_intval[1:0] r/w configures the dvs inter val for channel 1 00 = 62.5 s (default) 01 = 31.2 s 10 = 15.6 s 11 = 7.8 s
preliminary technical data ADP5051 rev. prb | page 49 of 63 register 6: opt_cfg (fpwm/psm mode and output discharge function configuration), address 0x06 register 6 is used to configure the operational mod e and the discharge switch setting for channel 1 to channel 4 . the psmx_on bit setting for each channel is in effect w hen the sync/mode pin is high (or when sync/mode is configu red as a clock input or output). when the sync/mode pin is low, all channels are forced to work in automatic pwm/ps m mode, and the psmx_on bit settings in this register are i gnored. the default value for the output discharge function can be programmed by factory fuse (output discharge function enabled or disabled for all four buck regulators). table 30. register 6 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dscg4_on dscg3_on dscg2_on dscg1_on psm4_on psm3_on psm2_on psm1_on table 31. opt_cfg register bit function description s bits bit name access description 7 dscg4_on r/w the default value is programmed by f actory fuse. 0 = disable output discharge function for channe l 4. 1 = enable output discharge function for channel 4. 6 dscg3_on r/w the default value is programmed by f actory fuse. 0 = disable output discharge function for channe l 3. 1 = enable output discharge function for channel 3. 5 dscg2_on r/w the default value is programmed by f actory fuse. 0 = disable output discharge function for channe l 2. 1 = enable output discharge function for channel 2. 4 dscg1_on r/w the default value is programmed by f actory fuse. 0 = disable output discharge function for channe l 1. 1 = enable output discharge function for channel 1. 3 psm4_on r/w this bit is ignored when the sync/mod e pin is low. 0 = enable forced pwm mode for channel 4 (defaul t). 1 = enable automatic pwm/psm mode for channel 4. 2 psm3_on r/w this bit is ignored when the sync/mod e pin is low. 0 = enable forced pwm mode for channel 3 (defaul t). 1 = enable automatic pwm/psm mode for channel 3. 1 psm2_on r/w this bit is ignored when the sync/mod e pin is low. 0 = enable forced pwm mode for channel 2 (defaul t). 1 = enable automatic pwm/psm mode for channel 2. 0 psm1_on r/w this bit is ignored when the sync/mod e pin is low. 0 = enable forced pwm mode for channel 1 (defaul t). 1 = enable automatic pwm/psm mode for channel 1.
ADP5051 preliminary technical data rev. prb | page 50 of 63 register 7: lch_cfg (shortcircuit latchoff and overvoltage latchoff configuration), address 0x07 register 7 is used to enable and disable the latch off function for the shortcircuit protection (scp) and the over voltage protection (ovp). when the scp or ovp latchoff function is enabled, the chx_lch bit in register 12 is set after an error co ndition occurs (see the latchoff protection section). the default value for the scp latchoff and ovp latchoff functions can be pr ogrammed by factory fuse (scp or ovp latchoff function enab led or disabled for all four buck regulators). table 32. register 7 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovp4_on ovp3_on ovp2_on ovp1_on scp4_on scp3_on scp 2_on scp1_on table 33. lch_cfg register bit function description s bits bit name access description 7 ovp4_on r/w the default value is programmed by fa ctory fuse. 0 = disable the ovp latchoff function for chann el 4. 1 = enable the ovp latchoff function for channe l 4. 6 ovp3_on r/w the default value is programmed by fa ctory fuse. 0 = disable the ovp latchoff function for chann el 3. 1 = enable the ovp latchoff function for channe l 3. 5 ovp2_on r/w the default value is programmed by fa ctory fuse. 0 = disable the ovp latchoff function for chann el 2. 1 = enable the ovp latchoff function for channe l 2. 4 ovp1_on r/w the default value is programmed by fa ctory fuse. 0 = disable the ovp latchoff function for chann el 1. 1 = enable the ovp latchoff function for channe l 1. 3 scp4_on r/w the default value is programmed by fa ctory fuse. 0 = disable the scp latchoff function for chann el 4. 1 = enable the scp latchoff function for channe l 4. 2 scp3_on r/w the default value is programmed by fa ctory fuse. 0 = disable the scp latchoff function for chann el 3. 1 = enable the scp latchoff function for channe l 3. 1 scp2_on r/w the default value is programmed by fa ctory fuse. 0 = disable the scp latchoff function for chann el 2. 1 = enable the scp latchoff function for channe l 2. 0 scp1_on r/w the default value is programmed by fa ctory fuse. 0 = disable the scp latchoff function for chann el 1. 1 = enable the scp latchoff function for channe l 1. register 8: sw_cfg (switching frequency and phase s hift configuration), address 0x08 register 8 is used to configure the switching frequ ency for channel 1 and channel 3 and to configure t he phase shift for channel 2, channel 3, and channel 4 with respect to channel 1 (0?). the default values for the channel 1 and chan nel 3 switching frequencies can be programmed by factory fuse. table 34. register 8 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 freq3 freq1 phase4[1:0] phase3[1:0] phase2[1:0] table 35. sw_cfg register bit function descriptions bits bit name access description 7 freq3 r/w the default value can be programmed by factory fuse.
preliminary technical data ADP5051 rev. prb | page 51 of 63 bits bit name access description 0 = switching frequency for channel 3 is the sam e as the master frequency set by the rt pin. 1 = switching frequency for channel 3 is half th e master frequency set by the rt pin. 6 freq1 r/w the default value can be programmed by factory fuse. 0 = switching frequency for channel 1 is the sam e as the master frequency set by the rt pin. 1 = switching frequency for channel 1 is half th e master frequency set by the rt pin. [5:4] phase4[1:0] r/w these bits configure the phas e shift for channel 4 with respect to channel 1 (0 ). 00 = 0 phase shift. 01 = 90 phase shift. 10 = 180 phase shift (default). 11 = 270 phase shift. [3:2] phase3[1:0] r/w these bits configure the phas e shift for channel 3 with respect to channel 1 (0 ). 00 = 0 phase shift (default). 01 = 90 phase shift. 10 = 180 phase shift. 11 = 270 phase shift. [1:0] phase2[1:0] r/w these bits configure the phas e shift for channel 2 with respect to channel 1 (0 ). 00 = 0 phase shift. 01 = 90 phase shift. 10 = 180 phase shift (default). 11 = 270 phase shift. register 9: th_cfg (temperature warning and low v in warning threshold configuration), address 0x09 register 9 is used to configure the junction temper ature overheat detection threshold and the low inpu t voltage detection threshold. when these thresholds are enabled, the temp_int and lvin_int status bits in register 14 are set if the thresholds are exceeded. table 36. register 9 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved temp_th[1:0] lvin_th[3:0] table 37. th_cfg register bit function descriptions bits bit name access description [7:6] reserved r/w reserved. [5:4] temp_th[1:0] r/w these bits set the junction temperature overheat threshold. 00 = temperature warning function disabled (defa ult). 01 = 105c. 10 = 115c. 11 = 125c. [3:0] lvin_th[3:0] r/w these bits set the low input voltage detection threshold. 0000 = 4.2 v (default). 0001 = 4.7 v. 0010 = 5.2 v. 0011 = 5.7 v. 0100 = 6.2 v. 0101 = 6.7 v. 0110 = 7.2 v. 0111 = 7.7 v. 1000 = 8.2 v. 1001 = 8.7 v. 1010 = 9.2 v.
ADP5051 preliminary technical data rev. prb | page 52 of 63 bits bit name access description 1011 = 9.7 v. 1100 = 10.2 v. 1101 = 10.7 v. 1110 = 11.2 v. 1111 = low input voltage warning function disabl ed. register 10: hiccup_cfg (hiccup configuration), add ress 0x0a register 10 is used to configure the sync/mode pin as a synchronization input or output and to configu re hiccup protection for each channel. the default value for hiccup protection ca n be programmed by factory fuse (hiccup function en abled or disabled for all four buck regulators). table 38. register 10 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sync_out reserved hiccup4_off hiccup3_off hiccup2_o ff hiccup1_off table 39. hiccup_cfg register bit function descript ions bits bit name access description 7 sync_out r/w the default value can be programmed by factory fuse. 0 = configure the sync/mode pin as a clock synch ronization input if a clock is connected (default). 1 = configure the sync/mode pin as a clock synch ronization output. [6:4] reserved r/w reserved. 3 hiccup4_off r/w the default value can be programm ed by factory fuse. 0 = enable hiccup protection for channel 4. 1 = disable hiccup protection for channel 4 (sho rtcircuit protection is disabled automatically). 2 hiccup3_off r/w the default value can be programm ed by factory fuse. 0 = enable hiccup protection for channel 3. 1 = disable hiccup protection for channel 3 (sho rtcircuit protection is disabled automatically). 1 hiccup2_off r/w the default value can be programm ed by factory fuse. 0 = enable hiccup protection for channel 2. 1 = disable hiccup protection for channel 2 (sho rtcircuit protection is disabled automatically). 0 hiccup1_off r/w the default value can be programm ed by factory fuse. 0 = enable hiccup protection for channel 1. 1 = disable hiccup protection for channel 1 (sho rtcircuit protection is disabled automatically).
preliminary technical data ADP5051 rev. prb | page 53 of 63 register 11: pwrgd_mask (channel mask configuration for pwrgd pin), address 0x0b register 11 is used to mask or unmask the powergoo d status of channel 1 to channel 4; when unmasked, a powergood failure on any of these channels triggers the pwrgd pin. th e output of the pwrgd pin represents the logical and of all unmasked pwrgd signals, that is, the pwrgd pin is pulled low by any pwrgd signal failure. there is a 1 ms validation de lay time before the pwrgd pin goes high. the default value for the powergood mask configuration can be programmed by factory fus e (mask function enabled or disabled for all four buck regu lators). table 40. register 11 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mask_ch4 mask_ch3 mask_ch2 mask_ch1 table 41. pwrgd_mask register bit function descript ions bits bit name access description [7:4] reserved r/w reserved. 3 mask_ch4 r/w the default value can be programmed by factory fuse. 0 = mask powergood status of channel 4. 1 = output powergood status of channel 4 to the pwrgd pin. 2 mask_ch3 r/w the default value can be programmed by factory fuse. 0 = mask powergood status of channel 3. 1 = output powergood status of channel 3 to the pwrgd pin. 1 mask_ch2 r/w the default value can be programmed by factory fuse. 0 = mask powergood status of channel 2. 1 = output powergood status of channel 2 to the pwrgd pin. 0 mask_ch1 r/w the default value can be programmed by factory fuse. 0 = mask powergood status of channel 1. 1 = output powergood status of channel 1 to the pwrgd pin. register 12: lch_status (latchoff status readback) , address 0x0c register 12 contains latched fault flags for therma l shutdown and channel latchoff caused by an ovp o r scp condition. latched flags are not reset when the fault disappears but are cleared only when 1 is written to the appropriate bit (if the fault no longer persists). table 42. register 12 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tsd_lch ch4_lch ch3_lch ch2_lch ch1_lch table 43. lch_status register bit function descript ions bits bit name access description [7:5] reserved r/w reserved. 4 tsd_lch read/selfclear 0 = no thermal shutdown h as occurred. 1 = thermal shutdown has occurred. 3 ch4_lch read/selfclear 0 = no shortcircuit or o vervoltage latchoff has occurred on channel 4. 1 = shortcircuit or overvoltage latchoff has o ccurred on channel 4. 2 ch3_lch read/selfclear 0 = no shortcircuit or o vervoltage latchoff has occurred on channel 3. 1 = shortcircuit or overvoltage latchoff has o ccurred on channel 3. 1 ch2_lch read/selfclear 0 = no shortcircuit or o vervoltage latchoff has occurred on channel 2. 1 = shortcircuit or overvoltage latchoff has o ccurred on channel 2. 0 ch1_lch read/selfclear 0 = no shortcircuit or o vervoltage latchoff has occurred on channel 1. 1 = shortcircuit or overvoltage latchoff has occu rred on channel 1.
ADP5051 preliminary technical data rev. prb | page 54 of 63 register 13: status_rd (status readback), address 0 x0d the readonly register 13 indicates the realtime s tatus of the powergood signals for channel 1 to ch annel 4 and mr button. table 44. register 13 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mr_st reserved pwrg4 pwrg3 pwrg2 pwrg1 table 45. status_rd register bit function descripti ons bits bit name access description 7 reserved r reserved. 6 mr_st r this bit is only active when the power on /off switch functionality is chosen. 0 = mr button was not pressed (default). 1 = mr button pressed (after 100 ns debounce timer). [5:4] reserved r reserved. 3 pwrg4 r 0 = channel 4 powergood status is low (d efault). 1 = channel 4 powergood status is high. 2 pwrg3 r 0 = channel 3 powergood status is low (d efault). 1 = channel 3 powergood status is high. 1 pwrg2 r 0 = channel 2 powergood status is low (d efault). 1 = channel 2 powergood status is high. 0 pwrg1 r 0 = channel 1 powergood status is low (d efault). 1 = channel 1 powergood status is high.
preliminary technical data ADP5051 rev. prb | page 55 of 63 register 14: int_status (interrupt status readback) , address 0x0e register 14 contains the interrupt status for the f ollowing events: junction temperature overheat warning, low input vo ltage warning, and powergood signal failure on channel 1 to chann el 4. when any of these unmasked events occur, the int pin is pulled low to indicate a fault condition. (masking of these events is configured in register 15.) to determine the cause of the fault, read this register. latched flags are no t reset when the fault disappears but are cleared only when 1 is wri tten to the appropriate bit or when all enx pins = 0. table 46. register 14 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mr_int temp_int lvin_int pwrg4_int pwrg3_i nt pwrg2_int pwrg1_int table 47. int_status register bit function descript ions bits bit name access description 7 reserved r/w reserved. 6 mr_int read/selfclear this bit is only active wh en the power on/off switch functionality is chosen. this bit indicates whether the mr button has been pressed. 0 = mr button was not pressed. 1 = mr button has been pressed. 5 temp_int read/selfclear this bit indicates wheth er the junction temperature threshold has been exce eded. 0 = junction temperature has not exceeded the th reshold. 1 = junction temperature has exceeded the thresh old. 4 lvin_int read/selfclear this bit indicates wheth er the low voltage input threshold has been exceede d. 0 = low voltage input has not fallen below the t hreshold. 1 = low voltage input has fallen below the thres hold. 3 pwrg4_int read/selfclear the powergood interrup t is masked when the part is initialized and during a normal shutdown. 0 = no powergood failure has been detected on c hannel 4. 1 = powergood failure has been detected on chan nel 4. 2 pwrg3_int read/selfclear the powergood interrup t is masked when the part is initialized and during a normal shutdown. 0 = no powergood failure has been detected on c hannel 3. 1 = powergood failure has been detected on chan nel 3. 1 pwrg2_int read/selfclear the powergood interrup t is masked when the part is initialized and during a normal shutdown. 0 = no powergood failure has been detected on c hannel 2. 1 = powergood failure has been detected on chan nel 2. 0 pwrg1_int read/selfclear the powergood interrup t is masked when the part is initialized and during a normal shutdown. 0 = no powergood failure has been detected on c hannel 1. 1 = powergood failure has been detected on chan nel 1. register 15: int_mask (interrupt mask configuration ), address 0x0f register 15 is used to mask or unmask various warni ngs for use by the interrupt ( int ) pin. when any bit in this register is masked, the associated event does not trigger the int pin. table 48. register 15 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved mask_mr mask_temp mask_lvin mask_pwrg4 mas k_pwrg3 mask_pwrg2 mask_pwrg1 table 49. int_mask register bit function descriptio ns bits bit name access description 7 reserved r/w reserved. 6 mask_mr r/w this register is only active when the power on/off switch functionality is chosen. 0 = mr button pressed does not trigger interrupt pin (def ault).
ADP5051 preliminary technical data rev. prb | page 56 of 63 bits bit name access description 1 = mr button pressed triggers interrupt pin. 5 mask_temp r/w 0 = temperature overheat warning do es not trigger the interrupt pin (default). 1 = temperature overheat warning triggers the in terrupt pin. 4 mask_lvin r/w 0 = low voltage input warning does not trigger the interrupt pin (default). 1 = low voltage input warning triggers the inter rupt pin. 3 mask_pwrg4 r/w 0 = powergood warning on channel 4 does not trigger the interrupt pin (default). 1 = powergood warning on channel 4 triggers the interrupt pin. 2 mask_pwrg3 r/w 0 = powergood warning on channel 3 does not trigger the interrupt pin (default). 1 = powergood warning on channel 3 triggers the interrupt pin. 1 mask_pwrg2 r/w 0 = powergood warning on channel 2 does not trigger the interrupt pin (default). 1 = powergood warning on channel 2 triggers the interrupt pin. 0 mask_pwrg1 r/w 0 = powergood warning on channel 1 does not trigger the interrupt pin (default). 1 = powergood warning on channel 1 triggers the interrupt pin. register 16: force_shut (forced shut down), address 0x10 register 16 is used to force all channels to shut d own and reset pctrl register by the i 2 c host. this register is only active when the power on/off switch functionality is chosen. table 50. register 16 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 force_shut[7:0] table 51. force_shut register bit function descript ions bits bit name access description [7:0] force_shut[7:0] w this register is only activ e when the power on/off switch functionality is cho sen. to shut down all channels and reset pctrl register, write 0xa9 t o this register. register 17: default_set (default reset), address 0 x11 the writeonly register 17 is used to reset all reg isters to their default values. table 52. register 17 bit assignments bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default_set[7:0] table 53. default_set register bit function descrip tions bits bit name access description [7:0] default_set[7:0] w to reset all registers to their default values, write 0x7f to this register.
preliminary technical data ADP5051 rev. prb | page 57 of 63 factory programmable options table 54 to table 70 list the options that can be p rogrammed into the ADP5051 when it is ordered from analog devices. for a list of the default options, see table 71. to ord er a device with options other than the default options, contact you r local analog devices sales or distribution representative. table 54. output voltage options for channel 1 (fix ed output options: 0.85 v to 1.6 v in 25 mv increments ) option description option 0 0.8 v adjustable output (default) option 1 0.85 v fixed output option 2 0.875 v fixed output option 30 1.575 v fixed output option 31 1.6 v fixed output table 55. output voltage options for channel 2 (fix ed output options: 3.3 v to 5.0 v in 300 mv/200 mv increments) option description option 0 0.8 v adjustable output (default) option 1 3.3 v fixed output option 2 3.6 v fixed output option 3 3.9 v fixed output option 4 4.2 v fixed output option 5 4.5 v fixed output option 6 4.8 v fixed output option 7 5.0 v fixed output table 56. output voltage options for channel 3 (fix ed output options: 1.2 v to 1.8 v in 100 mv increments ) option description option 0 0.8 v adjustable output (default) option 1 1.2 v fixed output option 2 1.3 v fixed output option 3 1.4 v fixed output option 4 1.5 v fixed output option 5 1.6 v fixed output option 6 1.7 v fixed output option 7 1.8 v fixed output table 57. output voltage options for channel 4 (fix ed output options: 2.5 v to 5.5 v in 100 mv increments ) option description option 0 0.8 v adjustable output (default) option 1 2.5 v fixed output option 2 2.6 v fixed output option 30 5.4 v fixed output option 31 5.5 v fixed output table 58. pin 20, pwrgd/a0 pin options option description option 0 pwrgd pin for powergood output (default) option 1 a0 pin for i 2 c address setting (see the i2c addresses section for additional information on the a0 pin) table 59. pwrgd output options option description option 0 no monitoring of any channel option 1 monitor channel 1 output (default) option 2 monitor channel 2 output option 3 monitor channel 1 and channel 2 outputs option 4 monitor channel 3 output option 5 monitor channel 1 and channel 3 outputs option 6 monitor channel 2 and channel 3 outputs option 7 monitor channel 1, channel 2, and channel 3 outputs option 8 monitor channel 4 output option 9 monitor channel 1 and channel 4 outputs option 10 monitor channel 2 and channel 4 outputs option 11 monitor channel 1, channel 2, and channel 4 outputs option 12 monitor channel 3 and channel 4 outputs option 13 monitor channel 1, channel 3, and channel 4 outputs option 14 monitor channel 2, channel 3, and channel 4 outputs option 15 monitor channel 1, channel 2, channel 3, and channel 4 outputs table 60. output discharge functionality options option description option 0 output discharge function disabled for all four buck regulators option 1 output discharge function enabled for all four buck regulators (default) table 61. switching frequency options for channel 1 option description option 0 1 switching frequency set by the rt pin (default) option 1 ? switching frequency set by the rt pin table 62. switching frequency options for channel 3 option description option 0 1 switching frequency set by the rt pin (default) option 1 ? switching frequency set by the rt pin table 63. pin 43, sync/mode pin options option description
ADP5051 preliminary technical data rev. prb | page 58 of 63 option 0 forced pwm/automatic pwm/psm mode setting with the ability to synchronize to an external cloc k (default) option 1 generate a clock signal equal to the maste r frequency set by the rt pin table 64. hiccup protection options for the four bu ck regulators option description option 0 hiccup protection enabled for overcurrent events (default) option 1 hiccup protection disabled; frequency fold back protection only for overcurrent events table 65. short-circuit latch-off options for the f our buck regulators option description option 0 latchoff function disabled for output sho rtcircuit events (default) option 1 latchoff function enabled for output shor tcircuit events table 66. overvoltage latch-off options for the fou r buck regulators option description option 0 latchoff function disabled for output ove rvoltage events (default) option 1 latchoff function enabled for output over voltage events table 67. reset timeout period options option description option 0 1.4 ms option 1 28 ms option 2 200 ms (default) option 3 1.6 sec table 68. watchdog timeout period options option description option 0 6.3 ms option 1 102 ms option 2 1.6 sec (default) option 3 25.6 sec table 69. manual reset input mode options option description option 0 processor manual reset mode (default) option 1 power on/off switch mode table 70. i 2 c address options option description option 0 0x4a (default) option 1 0x5a option 2 0x6a option 3 0x7a
preliminary technical data ADP5051 rev. prb | page 59 of 63 factory default options table 71 lists the factory default options programm ed into the ADP5051 when the device is ordered (see the ordering guide ). to order the device with options other than the def ault options, contact your local analog devices sales or distribu tion representative. table 54 to table 70 list all avail able options for the device. table 71. factory default options option default value channel 1 output voltage 0.8 v adjustable output channel 2 output voltage 0.8 v adjustable output channel 3 output voltage 0.8 v adjustable output channel 4 output voltage 0.8 v adjustable output pwrgd pin (pin 20) function pwrgd pin for powergood output pwrgd pin (pin 20) output monitor channel 1 output output discharge function enabled for all four buck regulators switching frequency on channel 1 1 switching frequency set by the rt pin switching frequency on channel 3 ? switching frequency set by the rt pin sync/mode pin (pin 43) function forced pwm/automatic pwm/psm mode setting with the ability to synchronize to an external clock hiccup protection enabled for overcurrent events shortcircuit latchoff function disabled for output shortcircuit events overvoltage latchoff function disabled for output overvoltage events reset timeout period 200 ms watchdog timeout period 1.6 sec manual reset input mode processor manual reset mode i 2 c address 0x4a
ADP5051 preliminary technical data rev. prb | page 60 of 63 outline dimensions 1 0.50 bsc bottom view top view pin 1 indicator 48 13 24 36 37 exposed pad p i n 1 i n d i c a t o r * 5.65 5.60 sq 5.55 0.50 0.40 0.30 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.20 04-26-2013-c 7.10 7.00 sq 6.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min * compliant to jedec standards mo-220-wkkd-2 with the exception of the exposed pad dimension. figure 67. 48-lead lead frame chip scale package [l fcsp_wq] 7 mm 7 mm body, very very thin quad (cp-48-13) dimensions shown in millimeters ordering guide model 1 temperature range package description package opti on 2 ADP5051acpzr7 ?40c to +125c 48lead lead frame c hip scale package [lfcsp_wq] cp4813 ADP5051evalz evaluation board 1 z = rohs compliant part. 2 table 71 lists the factory default options for the device. for a list of factory programmable options , see the factory programmable options section. to order a device with options other than the default options, contac t your local analog devices sales or distribution r epresentative.
preliminary technical data ADP5051 rev. prb | page 61 of 63 notes
ADP5051 preliminary technical data rev. prb | page 62 of 63 notes
preliminary technical data ADP5051 rev. prb | page 63 of 63 notes i 2 c refers to a communications protocol originally de veloped by philips semiconductors (now nxp semicond uctors). ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their re spective owners. pr1163509/13 (prb)

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